Semiconductor device and method for manufacturing the same

ABSTRACT

An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to a semiconductor device which has a circuit including a thin film transistor (hereinafter, referred to as a TFT) in which a channel formation region is formed using an oxide semiconductor film and a manufacturing method thereof. For example, the present invention relates to an electronic appliance in which an electro-optical device typified by a liquid crystal display panel or a light-emitting display device including an organic light-emitting element is mounted as its component.

Note that the semiconductor device in this specification indicates all the devices which can operate by using semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic appliance are all included in the semiconductor devices.

2. Description of the Related Art

In recent years, active matrix display devices (such as liquid crystal display devices, light-emitting display devices, or electrophoretic display devices) in which a switching element formed of a TFT is provided for each of display pixels arranged in a matrix have been actively developed. In the active matrix display devices, a switching element is provided for each of pixels (or each of dots), and thus, there is such an advantage that the active matrix display devices can be driven at lower voltage than passive matrix display devices in the case where the pixel density is increased.

In addition, a technique has attracted attention, where a thin film transistor (TFT) in which a channel formation region is formed using an oxide semiconductor film, or the like is manufactured and such a TFT or the like is applied to electronic devices or optical devices. For example, a TFT in which zinc oxide (ZnO) is used as an oxide semiconductor film or a TFT in which InGaO₃(ZnO)_(m) is used as an oxide semiconductor film can be given. A technique in which a TFT including such an oxide semiconductor film is formed over a light-transmitting substrate and used as a switching element or the like of an image display device, is disclosed in Reference 1 and Reference 2.

REFERENCE Patent Document

-   Reference 1: Japanese Published Patent Application No. 2007-123861 -   Reference 2: Japanese Published Patent Application No. 2007-096055

SUMMARY OF THE INVENTION

For a thin film transistor in which a channel formation region is formed using an oxide semiconductor film, high speed operation, a comparatively-easy manufacturing process, and sufficient reliability are required.

In formation of a thin film transistor, a low resistance metal material is used for a source and drain electrodes. In particular, when a display device with a large-area display is manufactured, a problem of signal delay due to resistance of a wiring significantly arises. Accordingly, it is preferable that a metal material with a low electric resistance value be used for a material of a wiring and an electrode. In a thin film transistor having a structure in which an oxide semiconductor film and a source and drain electrodes formed using a metal material with a low electric resistance value are in direct contact with each other, there is a concern that contact resistance increases. One of conceivable reasons for increase of contact resistance is to form Schottky junction in a contact surface between the source and drain electrodes and the oxide semiconductor film.

In addition, capacitance is formed in a portion where the source and drain electrodes and the oxide semiconductor film have a direct contact with each other, and there are risks that frequency characteristics (called “f characteristics”) decrease and high speed operation of the thin film transistor is hindered.

An object is to provide a thin film transistor and a manufacturing method thereof, in which an oxide semiconductor film containing indium (In), gallium (Ga), and zinc (Zn) is used and the contact resistance of a source or drain electrode is reduced.

Another object is to improve operation characteristics and reliability of the thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used.

Further, another object is to reduce variation in electric properties of the thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used. In particular, in a liquid crystal display device where variation between elements is large, there is a risk that display unevenness due to variation in the TFT characteristics is caused.

Further, in a display device including a light-emitting element, in the case where there is large variation in ON current (I on) of TFTs (TFTs provided in a driver circuit or TFTs supplying current to light-emitting elements arranged in pixels) arranged so as to make constant current flow in a pixel electrode, a display screen has a risk of generation of variation in luminance therein.

The present invention aims to achieve at least one of the above-described objects.

An embodiment of the present invention is an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers.

In this specification, a semiconductor layer formed using an oxide semiconductor film containing In, Ga, and Zn is also referred to as an “IGZO semiconductor layer”.

Ohmic contact is needed between the source electrode layer and the IGZO semiconductor layer and moreover, its contact resistance is preferably reduced as much as possible. Similarly, ohmic contact is needed between the drain electrode layer and the IGZO semiconductor layer, and its contact resistance is preferably reduced as much as possible.

Thus, a buffer layer with higher carrier concentration than the IGZO semiconductor layer is intentionally provided between the source and drain electrode layers and the IGZO semiconductor layer, so that ohmic contact is formed.

As the buffer layer, an oxide semiconductor film containing In, Ga, and Zn, which has n-type conductivity (hereinafter, referred to as “n-type oxide semiconductor film”) is used. An impurity element imparting n-type conductivity may be contained in the buffer layer. As the impurity element, for example, magnesium, aluminum, titanium, iron, tin, calcium, germanium, scandium, yttrium, zirconium, hafnium, boron, thallium, lead, or the like can be used. When magnesium, aluminum, titanium, or the like is contained in the buffer layer, a blocking effect against oxygen is generated, and oxygen concentration of the semiconductor layer can be kept within an optimal range by heat treatment or the like after film formation.

The buffer layer functions as an n⁺ layer and can also be referred to as a source and drain regions.

In order to reduce variation in electric properties of the thin film transistor, it is preferable that the IGZO semiconductor layer have an amorphous state.

An embodiment of a semiconductor device of the present invention includes a thin film transistor which includes a gate electrode layer, a gate insulating layer over the gate electrode layer, a semiconductor layer over the gate insulating layer, a first n-type buffer layer and a second n-type buffer layer over the semiconductor layer, and a source electrode layer over the first n-type buffer layer and a drain electrode layer over the second n-type buffer layer. Each of the semiconductor layer, the first n-type buffer layer and the second n-type buffer layer comprises oxide semiconductor containing indium, gallium, and zinc. Each carrier concentration of the first n-type buffer layer and the second n-type buffer layer is higher than that of the semiconductor layer. The semiconductor layer and the source electrode layer are electrically connected to each other with the first n-type buffer layer interposed therebetween, and the semiconductor layer and the drain electrode layers are electrically connected to each other with the second n-type buffer layer interposed therebetween.

Another embodiment of a semiconductor device of the present invention includes a thin film transistor which includes a gate electrode layer, a gate insulating layer over the gate electrode layer, a semiconductor layer over the gate insulating layer, a first n-type buffer layer and a second n-type buffer layer over the semiconductor layer, and a source electrode layer over the first n-type buffer layer and a drain electrode layer over the second n-type buffer layer. Each of the semiconductor layer, the first n-type buffer layer and the second n-type buffer layer comprises oxide semiconductor layer containing indium, gallium, and zinc. A region of the semiconductor layer between the first n-type buffer layer and the second n-type buffer layer is thinner than a region of the semiconductor layer under the first n-type buffer layer and a region of the semiconductor layer under the second n-type buffer layer. Each carrier concentration of the first n-type buffer layer and the second n-type buffer layer is higher than that of the semiconductor layer. The semiconductor layer and the source electrode layer are electrically connected to each other with the first n-type buffer layer interposed therebetween, and the semiconductor layer and the drain electrode layers are electrically connected to each other with the second n-type buffer layer interposed therebetween.

In the above structure, the thin film transistor further includes a third buffer layer and a fourth buffer layer each having the carrier concentration which is higher than the semiconductor layer but lower than each of the first n-type buffer layer and the second n-type buffer layer may be provided. The third buffer layer is provided between the semiconductor layer and the first n-type buffer layer, and the fourth buffer layer is provided between the semiconductor layer and the second n-type buffer layer. Each of the third buffer layer and the fourth buffer layer functions as an n⁻ layer.

The oxide semiconductor film (IGZO film) containing In, Ga, and Zn has such a characteristic that the hole mobility becomes higher as the carrier concentration becomes higher. Thus, the carrier concentration and the hole mobility in the oxide semiconductor film containing In, Ga, and Zn have a relation shown in FIG. 27. It is preferable that an IGZO film appropriate for a channel of a semiconductor layer have a carrier concentration (a concentration range 1 of a channel) lower than 1×10¹⁷ atoms/cm³ (more preferably, 1×10¹¹ atoms/cm³ or higher) and an IGZO film appropriate for a buffer layer have a carrier concentration (a concentration range 2 of a buffer layer) of 1×10¹⁸ atoms/cm³ or higher (1×10²² atoms/cm³ or lower). In the case of a semiconductor layer, the carrier concentration of the above IGZO film is a value in a condition at room temperature where source, drain, and gate voltages are not applied.

If the carrier concentration range of the IGZO film for a channel exceeds the above range, a thin film transistor has a risk of being normally on. Thus, with use of the IGZO film within a carrier concentration range disclosed in this specification as a channel of a semiconductor layer, a highly reliable thin film transistor can be provided.

In addition, a titanium film is preferably used as a source and drain electrode layers. For example, a stacked layer of a titanium film, an aluminum film, and a titanium film has low resistance, and hillock is hardly generated in the aluminum film.

According to an embodiment of a method for manufacturing a semiconductor device of the present invention, a gate electrode layer is formed over a substrate, a gate insulating layer is formed over the gate electrode layer, a semiconductor layer is formed over the gate insulating layer, a first n-type buffer layer and a second n-type buffer layer are formed over the semiconductor layer, and a source electrode layer is formed over the first n-type buffer layer and a drain electrode layer is formed over the second n-type buffer layer. Each of the semiconductor layer, the first n-type buffer layer and the second n-type buffer layer is formed using oxide semiconductor containing indium, gallium, and zinc. Each carrier concentration of the first n-type buffer layer and the second n-type buffer layer is higher than that of the semiconductor layer. The semiconductor layer and the source electrode layer are electrically connected to each other with the first n-type buffer layer interposed therebetween, and the semiconductor layer and the drain electrode layers are electrically connected to each other with the second n-type buffer layer interposed therebetween.

The gate insulating layer, the semiconductor layer, the first n-type buffer layer, the second n-type buffer layer, and the source and drain electrode layers can be successively formed without exposure to air. Successive formation contributes to reduction of defects caused by entry of impurities to be dust into an interface from air.

The gate insulating layer, the semiconductor layer, the first n-type buffer layer, the second n-type buffer layer, and the source and drain electrode layers may be formed by a sputtering method. It is preferable that the gate insulating layer and the semiconductor layer be formed in an oxygen atmosphere (or an atmosphere which contains oxygen of 90% or higher and a rare gas (argon) of 10% or lower) and that the first n-type buffer layer and the second n-type buffer layer be formed in a rare gas (argon) atmosphere.

Successive formation by a sputtering method as described above makes productivity improve and reliability of a thin film interface stable. Further, by forming the gate insulating layer and the semiconductor layer in an oxygen atmosphere so that a large amount of oxygen is contained, it is possible to suppress reduction in reliability due to deterioration, shift of the thin film transistor characteristics toward the normally on side, and the like.

According to an embodiment of a method for manufacturing a semiconductor device of the present invention, a gate electrode layer is formed over a substrate, a gate insulating layer is formed over the gate electrode layer, a semiconductor layer is formed over the gate insulating layer, a first n-type buffer layer and a second n-type buffer layer are formed over the semiconductor layer, and a source electrode layer is formed over the first n-type buffer layer and a drain electrode layer is formed over the second n-type buffer layer. Each of the semiconductor layer, the first n-type buffer layer and the second n-type buffer layer is formed using oxide semiconductor containing indium, gallium, and zinc. Each carrier concentration of the first n-type buffer layer and the second n-type buffer layer is higher than that of the semiconductor layer. The semiconductor layer and the source electrode layer are electrically connected to each other with the first n-type buffer layer interposed therebetween, and the semiconductor layer and the drain electrode layers are electrically connected to each other with the second n-type buffer layer interposed therebetween. The gate insulating layer, the semiconductor layer, the first n-type buffer layer, the second n-type buffer layer and the source and drain electrode layers are successively formed without exposure to air.

According to an embodiment of the present invention, a thin film transistor with small photoelectric current, small parasitic capacitance, and high on-off ratio can be obtained, so that a thin film transistor having excellent dynamic characteristics can be manufactured. Therefore, a semiconductor device which includes thin film transistors having high electric properties and high reliability can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1D illustrate a semiconductor device.

FIGS. 2A and 2B illustrate a semiconductor device.

FIGS. 3A to 3G illustrate a method for manufacturing a semiconductor device.

FIGS. 4A to 4D illustrate a method for manufacturing a semiconductor device.

FIGS. 5A and 5B illustrate a semiconductor device.

FIGS. 6A and 6B illustrate a semiconductor device.

FIGS. 7A and 7B illustrate a semiconductor device.

FIG. 8 illustrates a semiconductor device.

FIGS. 9A and 9B illustrate a semiconductor device.

FIGS. 10A to 10D illustrate a method for manufacturing a semiconductor device.

FIG. 11 illustrates a semiconductor device.

FIGS. 12A and 12B are block diagrams each illustrating a semiconductor device.

FIG. 13 illustrates a configuration of a signal line driver circuit.

FIG. 14 is a timing chart illustrating operation of a signal line driver circuit.

FIG. 15 is a timing chart illustrating operation of a signal line driver circuit.

FIG. 16 illustrates a configuration of a shift register.

FIG. 17 illustrates a connection of a flip-flop illustrated in FIG. 16.

FIG. 18 is a top schematic view of a multi-chamber manufacturing apparatus.

FIGS. 19A and 19B illustrate a semiconductor device.

FIGS. 20A to 20C illustrate a semiconductor device.

FIG. 21 illustrates a semiconductor device.

FIGS. 22A and 22B illustrate a semiconductor device.

FIG. 23 illustrates a semiconductor device.

FIGS. 24A to 24C each illustrate a semiconductor device.

FIGS. 25A and 25B illustrate a semiconductor device.

FIG. 26 illustrates a semiconductor device.

FIG. 27 is a graph showing a relation between the hole mobility and the carrier concentration.

FIGS. 28A and 28B each illustrate an example of a usage pattern of electronic paper.

FIG. 29 is an external view illustrating an example of an e-book reader.

FIG. 30A is an external view illustrating an example of a television device and FIG. 30B is an external view of an example of a digital photo frame.

FIGS. 31A and 31B are external views each illustrating an example of an amusement machine.

FIG. 32 is an external view illustrating an example of a mobile phone set.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments will be described in detailed with reference to the accompanying drawings. However, the present invention is not limited to the following description, and various changes and modifications for the modes and details thereof will be apparent to those skilled in the art unless such changes and modifications depart from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to what is described in the embodiments described below. Identical portions or portions having similar functions are marked by same reference numerals throughout the drawings so as to omit repeated explanation.

Embodiment 1

In this embodiment, a thin film transistor and a manufacturing process thereof will be described with reference to FIGS. 1A to 1D, FIGS. 2A and 2B, FIGS. 3A to 3Q and FIGS. 4A to 4D.

Thin film transistors 170 a, 170 b, and 170 c each having a bottom gate structure of this embodiment are illustrated in FIGS. 1A to 1D and FIGS. 2A and 2B. FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along a line A1-A2 of FIG. 1A. FIG. 1C is a plan view and FIG. 1D is a cross-sectional view taken along a line B1-B2 of FIG. 1C. FIG. 2A is a plan view and FIG. 2B is a cross-sectional view taken along a line C1-C2 of FIG. 2A.

In FIGS. 1A and 1, over a substrate 100, the thin film transistor 170 a which includes a gate electrode layer 101, a gate insulating layer 102, a semiconductor layer 103, n-type buffer layers 104 a and 104 b, and a source and drain electrode layers 105 a and 105 b is provided.

As the semiconductor layer 103, an oxide semiconductor film containing In, Ga, and Zn is used. The buffer layers 104 a and 104 b having higher carrier concentration than the semiconductor layer 103 are intentionally provided between the source and drain electrode layers 105 a and 105 b and the semiconductor layer 103 which is an IGZO semiconductor layer, whereby an ohmic contact is formed.

As the buffer layers 104 a and 104 b, an n-type oxide semiconductor film containing In, Ga, and Zn is used. An impurity element imparting n-type conductivity may be contained in the buffer layers 104 a and 104 b. As an example of the impurity element, magnesium, aluminum, titanium, iron, tin, calcium, germanium, scandium, yttrium, zirconium, hafnium, boron, thallium, lead, or the like can be used. A buffer layer containing magnesium, aluminum, titanium, or the like has a blocking effect against oxygen, and the oxygen concentration of the semiconductor layer can be kept within the optimal range by heat treatment after film formation.

In this embodiment, it is preferable that the semiconductor layer have a carrier concentration lower than 1×10¹⁷ atoms/cm³ (more preferably, 1×10¹¹ atoms/cm³ or higher) and that the buffer layer have a carrier concentration of 1×10¹⁸ atoms/cm³ or higher (1×10²² atoms/cm³ or lower).

If the carrier concentration range of the IGZO film for a channel exceeds the above range, the thin film transistor has a risk of being normally on. Thus, with use of the IGZO film having the carrier concentration range of this embodiment as a channel of the semiconductor layer, a highly reliable thin film transistor can be obtained.

In a case where a second buffer layer having a carrier concentration which is lower than the buffer layer functioning as an n⁺ layer but higher than the semiconductor layer is provided between the semiconductor layer and the buffer layer, the carrier concentration of the second buffer layer may be set intermediate between the carrier concentration of the semiconductor layer and the carrier concentration of the buffer layer.

The buffer layers 104 a and 104 b function as an n⁺ layer and can also be referred to as source and drain regions. Note that each end portion of the buffer layers 104 a and 104 b has a tapered shape, and each plan view of FIG. 1A and FIG. 1C illustrates upper end portions of the buffer layers 104 a and 104 b having a tapered shape. Thus, although the plan views of FIG. 1A and FIG. 1C illustrate that end portions of the gate electrode layer 101 and end portions of the buffer layers 104 a and 104 b are aligned, the gate electrode layer 101 and the buffer layers 104 a and 104 b partly overlap with each other as illustrated in FIG. 1B and FIG. 1D. This is the same as in the other drawings of this specification.

In the case of the thin film transistor 170 a of FIG. 1A and FIG. 1B, the buffer layers 104 a and 104 b and the source and drain electrode layers 105 a and 105 b are processed by etching with use of different masks, so that the buffer layers 104 a and 104 b and the source and drain electrode layers 105 a and 105 b have different shapes from each other.

In the case of the thin film transistor 170 b of FIG. 1C and FIG. 1D, the buffer layers 104 a and 104 b and the source and drain electrode layers 105 a and 105 b are processed by etching with use of the same mask, so that the buffer layers 104 a and 104 b and the source and drain electrode layers 105 a and 105 b have the same or substantially the same shape.

In the case of the thin film transistor 170 a of FIGS. 1A and 1B and the thin film transistor 170 b of FIG. 1C and FIG. 1D, end portions of the source and drain electrode layers 105 a and 105 b are not aligned with the end portions of the buffer layers 104 a and 104 b over the semiconductor layer 103, so that the buffer layers 104 a and 104 b are partly exposed.

On the other hand, in the case of the thin film transistor 170 c of FIGS. 2A and 2B, the semiconductor layer 103 and the buffer layers 104 a and 104 b are processed by etching with use of the same mask, so that end portions of the semiconductor layer 103 and end portions of the buffer layers 104 a and 104 b are aligned. Note that in the thin film transistor 170 c of FIGS. 2A and 2B, end portions of the source and drain electrode layers 105 a and 105 b are also aligned with the end portions of the buffer layers 104 a and 104 b over the semiconductor layer 103.

Furthermore, a thin film transistor 170 d in which a source and drain electrode layers have a layered structure is illustrated in FIG. 11. The thin film transistor 170 d has a structure in which a source and drain electrode layers 105 al and 105 b 1, a source and drain electrode layers 105 a 2 and 105 b 2, and a source and drain electrode layers 105 a 3 and 105 b 3 are stacked. For example, a titanium film can be used as the source and drain electrode layers 105 al and 105 b 1, an aluminum film as the source and drain electrode layers 105 a 2 and 105 b 2, and a titanium film as the source and drain electrode layers 105 a 3 and 105 b 3.

In the case of the thin film transistor 170 d, the source and drain electrode layers 105 a 3 and 105 b 3 are formed by wet etching, and the source and drain electrode layers 105 a 2 and 105 b 2 are formed by wet etching while using the source and drain electrode layers 105 al and 105 b 1 as an etching stopper. With use of the same mask in the above wet etching, the source and drain electrode layers 105 al and 105 b 1, the buffer layers 104 a and 104 b, the semiconductor layer 103 are formed by dry etching.

Accordingly, end portions of the source and drain electrode layers 105 al and 105 b 1 are aligned with end portions of the buffer layers 104 a and 104 b, respectively. End portions of the source and drain electrode layers 105 a 2 and 105 b 2 and end portions of the source and drain electrode layers 105 a 3 and 105 b 3 are positioned more inwardly than the end portions of the source and drain electrode layers 105 al and 105 bi.

As described above, in the case where etching selectively of the conductive film used for the source and drain electrode layers to the buffer layer and the semiconductor layer is low, a conductive film functioning as an etching stopper may be stacked and etching may be performed plural times with use of different etching conditions.

A method for manufacturing the thin film transistor 170 a of FIGS. 1A and 1B is described with reference to FIGS. 3A to 3G.

Over the substrate 100, the gate electrode layer 101, the gate insulating layer 102, and the semiconductor film 111 are formed (see FIG. 3A). As the substrate 100, any of the following substrates can be used: non-alkaline glass substrates made of barium borosilicate glass, aluminoborosilicate glass, aluminosilicate glass, and the like by a fusion method or a float method; ceramic substrates; plastic substrates having heat resistance enough to withstand a process temperature of this manufacturing process; and the like. Alternatively, a metal substrate such as a stainless steel alloy substrate, provided with an insulating film over its surface, may also be used. The substrate 100 may have a size of 320 mm×400 mm, 370 mm×470 mm, 550 mm×650 mm, 600 mm×720 mm, 680 mm×880 mm, 730 mm×920 mm, 1000 mm×1200 mm, 1100 mm×1250 mm, 1150 mm×1300 mm, 1500 mm×1800 mm, 1900 mm×2200 mm, 2160 mm×2460 mm, 2400 mm×2800 mm, 2850 mm×3050 mm, or the like.

In addition, an insulating film as a base film may be formed over the substrate 100. The base film may be formed with a single layer or stacked layer of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and/or a silicon nitride oxide film by a CVD method, a sputtering method, or the like.

The gate electrode layer 101 is formed using a metal material such as titanium, molybdenum, chromium, tantalum, tungsten, or aluminum, or an alloy material thereof. The gate electrode layer 101 can be formed in such a manner that a conductive film is formed over the substrate 100 by a sputtering method or a vacuum evaporation method; a mask is formed over the conductive film by a photolithography technique or an inkjet method; and the conductive film is etched using the mask. Alternatively, the gate electrode layer 101 can be formed by discharging a conductive nanopaste of silver, gold, copper, or the like by an inkjet method and baking it. Note that, as barrier metal which increases adhesion of the gate electrode layer 101 and prevents diffusion of a formation material of the gate electrode layer 101 to the substrate and the base film, a nitride film of the above-mentioned metal material may be provided between the substrate 100 and the gate electrode layer 101. The gate electrode layer 101 may have a single-layer structure or a layered structure. For example, a structure in which a molybdenum film and an aluminum film are stacked in this order, a structure in which a molybdenum film and an alloy film of aluminum and neodymium are stacked in this order, a structure in which a titanium film and an aluminum film are stacked in this order, a structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order, or the like can be formed over the substrate 100.

Note that, because a semiconductor film and a wiring are to be formed over the gate electrode layer 101, it is preferable that the gate electrode layer 101 be processed to have tapered end portions in order to prevent disconnection.

The gate insulating layer 102 and the semiconductor film 111 can be formed successively without exposure to air. By successive formation, each interface between the stacked layers can be formed without being contaminated by atmospheric components or contaminating impurities contained in the atmosphere.

In an active matrix display device, electric properties of thin film transistors included in a circuit are important, and performance of the display device depends on the electric properties. In particular, the threshold voltage (Vth) is important in the electric properties of the thin film transistor. Even if the field-effect mobility is high, when the threshold voltage value is high or the threshold voltage value is on the minus side it is difficult to control the circuit. When the threshold voltage value is high and the absolute value of the threshold voltage is large in the thin film transistor, the thin film transistor driving at low voltage cannot perform switching function and may be a load. Further, in the case where the threshold voltage value is on the minus side, current tends to flow between the source electrode and the drain electrode even when the gate voltage is 0V; in other words, the thin film transistor tends to be normally on.

In the case of an n-channel thin film transistor, it is preferable that a channel be formed and drain current begin to flow after the positive voltage is applied as the gate voltage. A transistor in which a channel is not formed unless the driving voltage is increased and a transistor in which a channel is formed and drain current flows even in the case of the negative voltage state are unsuitable for a thin film transistor used in a circuit.

Thus, it is preferable that a channel be formed at a threshold voltage which is a positive value and as close to 0V as possible, of a gate voltage in a thin film transistor using an oxide semiconductor film containing In, Ga, and Zn.

An interface of the oxide semiconductor layer, that is, an interface between the oxide semiconductor layer and the gate insulating layer is considered to greatly affect the threshold voltage of the thin film transistor.

Thus, by formation of the interface in a clean condition, in addition to improving electric properties of the thin film transistor, the manufacturing process can be prevented from being complicated, so that a thin film transistor provided with improved mass productivity and high performance is achieved.

In particular, in the case where moisture from air is present in an interface between the oxide semiconductor layer and the gate insulating layer, problems arise in that the electric properties of the thin film transistor is degraded, the threshold voltages vary, and the thin film transistor tends to be normally on. Successive formation of the oxide semiconductor layer and the gate insulating layer excludes hydrogen compounds.

Thus, the gate insulating layer 102 and the semiconductor film 111 are successively formed under reduced pressure by a sputtering method without exposure to air, whereby a thin film transistor having an excellent interface, reduced leakage current, and high current driving capability can be achieved.

Further, the gate insulating layer 102 and the semiconductor film 111 which is an oxide semiconductor film containing In, Ga, and Zn are preferably formed in an oxygen atmosphere (or an atmosphere containing oxygen of 90% or higher and a rare gas such as argon or helium of 10% or lower).

By successive formation with use of a sputtering method in such a manner, productivity is increased and reliability of a thin film interface is stable. Furthermore, the gate insulating layer and the semiconductor layer are formed in an oxygen atmosphere so that a large amount of oxygen is contained, it is possible to suppress the reduction in reliability due to deterioration and the thin film transistor to be normally on.

The gate insulating layer 102 can be formed by a CVD method, a sputtering method, or the like using a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. In the thin film transistor 170 c illustrated in FIGS. 2A and 2B, the gate insulating layer 102 has a layered structure.

The gate insulating layer 102 can be formed by stacking a silicon nitride film or a silicon nitride oxide film, and a silicon oxide film or a silicon oxynitride film in this order. Note that the gate insulating layer can be formed by stacking not two layers but three layers of a silicon nitride film or a silicon nitride oxide film, a silicon oxide film or a silicon oxynitride film, and a silicon nitride film or a silicon nitride oxide film in this order from the substrate side. Alternatively, the gate insulating layer 102 can be formed with a single layer of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film.

As the gate insulating layer 102, a silicon nitride film may be formed over the gate electrode layer 101 by a plasma CVD method and a silicon oxide film may be formed by a sputtering method over the silicon nitride film. Alternatively, a silicon nitride film and a silicon oxide film may be sequentially stacked over the gate electrode layer 101 by a plasma CVD method, and a silicon oxide film may be further formed over the silicon oxide film by a sputtering method.

Here, a silicon oxynitride film means a film that contains more oxygen than nitrogen and includes oxygen, nitrogen, silicon, and hydrogen at concentrations ranging from 55 at. % to 65 at. %, 1 at. % to 20 at. %, 25 at. % to 35 at. %, and 0.1 at. % to 10 at. %, respectively. Further, a silicon nitride oxide film means a film that contains more nitrogen than oxygen and includes oxygen, nitrogen, silicon, and hydrogen at concentrations ranging from 15 at. % to 30 at. %, 20 at. % to 35 at. %, 25 at. % to 35 at. %, and 15 at. % to 25 at. %, respectively.

Alternatively, the gate insulating layer 102 may be formed using one kind of oxide, nitride, oxynitride, or nitride oxide of aluminum, yttrium, or hafnium; or a compound including at least two or more kinds of the aforementioned compounds.

A halogen element such as chlorine or fluorine may be contained in the gate insulating layer 102. The concentration of the halogen element in the gate insulating layer 102 may be from 1×10⁵ atoms/cm³ to 1×10² atoms/cm³ inclusive at the concentration peak.

As the semiconductor film 111, an oxide semiconductor film containing In, Ga, and Zn is formed. For example, as the semiconductor film 111, an oxide semiconductor film containing In, Ga, and Zn is formed to a thickness of 50 nm by a sputtering method. As specific example conditions, an oxide semiconductor target of 8 inches in diameter containing In, Ga, and Zn is used, a distance between a substrate and the target is set to 170 mm, and deposition is performed with direct-current (DC) power source of 0.5 kW at pressure of 0.4 Pa in an argon or oxygen atmosphere. Further, with use of pulse direct-current (DC) power source, dust can be reduced and the thickness becomes uniform, which is preferable.

Next, with use of a mask 113, the semiconductor film 111 is processed by etching to form a semiconductor layer 112 (see FIG. 3B). The semiconductor layer 112 can be formed by etching the semiconductor film 111 with use of the mask 113 which is formed by a photolithography technique or a droplet discharging method.

The semiconductor layer 112 is etched to have a tapered shape at an end portion, whereby disconnection of a wiring due to a step shape can be prevented.

Next, an n-type semiconductor film 114 which is an n-type oxide semiconductor film containing In, Ga, and Zn, is formed over the gate insulating layer 102 and the semiconductor layer 112 (see FIG. 3C). A mask 116 is formed over the n-type semiconductor film 114. The mask 116 is formed by a photolithography technique or an ink-jet method. With use of the mask 116, the n-type semiconductor film 114 is processed by etching to form an n-type semiconductor film 115 (see FIG. 3D). The n-type semiconductor film 115 may have a thickness of 2 nm to 100 nm (preferably, 20 nm to 50 nm). It is preferable to form the n-type semiconductor film 114 in a rare gas (preferably, argon) atmosphere.

As a formation method other than a sputtering method, of the oxide semiconductor films such as the semiconductor film 111 and the n-type semiconductor film 115, vapor phase methods such as a pulsed laser deposition method (a PLD method) and an electron beam deposition method can be used. Among vapor phase methods, a PLD method is suitable in terms of easy control of the composition of materials and a sputtering method is suitable in terms of mass productivity as described above.

In etching of the IGZO semiconductor films such as the semiconductor film 111 and the n-type semiconductor film 115, organic acid such as citric acid or oxalic acid can be used for etchant. For example, the semiconductor film 111 with a thickness of 50 nm can be processed by etching with use of ITO07N (manufactured by KANTO CHEMICAL CO., INC.) in 150 seconds.

A conductive film 117 is formed over the n-type semiconductor film 115 (see FIG. 3E).

The conductive film 117 is preferably formed using a single layer or a stacked layer of aluminum, copper, or an aluminum alloy to which an element improving heat resistance or an element preventing a hillock such as silicon, titanium, neodymium, scandium, or molybdenum is added. Alternatively, the conductive film 117 may have a layered structure where a film on the side in contact with the n-type semiconductor film is formed of titanium, tantalum, molybdenum, tungsten, or nitride of any of these elements and an aluminum film or an aluminum alloy film is formed thereover. Further alternatively, the conductive film 117 may have a layered structure where top and bottom surfaces of aluminum or an aluminum alloy are each covered with titanium, tantalum, molybdenum, tungsten, or nitride thereof. Here, a layered conductive film of a titanium film, an aluminum film, and a titanium film is used as the conductive film 117.

A stacked layer of a titanium film, an aluminum film, and a titanium film has low resistance and hillock is hardly generated in the aluminum film.

The conductive film 117 is formed by a sputtering method or a vacuum evaporation method. Alternatively, the conductive film 117 may be formed by discharging a conductive nanopaste of silver, gold, copper, or the like by a screen printing method, an ink-jet method, or the like and baking it.

Next, a mask 118 is formed over the conductive film 117. The conductive film 117 is etched with use of the mask 118 to be separated, so that the source and drain electrode layers 105 a and 105 b are formed (see FIG. 3F). As illustrated in FIG. 3F of this embodiment, the conductive film 117 is subjected to wet etching, whereby the conductive film 117 is isotropically etched. Thus, end portions of the source and drain electrode layers 105 a and 105 b are not aligned with end portions of the mask 118, and the end portions of the source and drain electrode layers 105 a and 105 b are positioned more inwardly. Next, the n-type semiconductor film 115 is etched with use of the mask 118 to form the buffer layers 104 a and 104 b (see FIG. 3G). Note that, depending on the etching condition, in the etching step of the n-type semiconductor film 115, the exposed region of the semiconductor layer 112 is partly etched, so that the semiconductor layer 103 is formed. Accordingly, a channel region of the semiconductor layer 103 between the buffer layers 104 a and 104 b is a region with a small thickness as illustrated in FIG. 3G. The region with a small thickness in the semiconductor layer 103 which is an IGZO semiconductor layer has a thickness of from 2 nm to 200 nm inclusive, preferably from 20 nm to 150 nm inclusive.

In addition, the semiconductor layer 103 may be subjected to plasma treatment. By plasma treatment, the semiconductor layer 103 damaged by etching can be recovered. It is preferable to perform plasma treatment in an O₂ or N₂O atmosphere, preferably, an N₂, He, or Ar atmosphere containing oxygen. Alternatively, plasma treatment may be performed in an atmosphere where Cl₂ or CF₄ is added to the above atmosphere. Note that it is preferable that plasma treatment be performed with non-bias applied.

The end portions of the buffer layers 104 a and 104 b are not aligned with the end portions of the source and drain electrode layers 105 a and 105 b, the end portions of the buffer layers 104 a and 104 b are formed more outwardly than the end portions of the source and drain electrode layers 105 a and 105 b.

After that, the mask 118 is removed. Through the above steps, the thin film transistor 170 a can be formed.

Next, the manufacturing steps of the thin film transistor 170 b of FIGS. 1C and 1D are described with reference to FIGS. 4A to 4D.

FIG. 4A illustrates a state in which the mask 113 is removed after the step of FIG. 3B. The n-type semiconductor film 114 and a conductive film 121 are sequentially stacked over the semiconductor layer 112 (see FIG. 4B). In this case, the n-type semiconductor film 114 and the conductive film 121 can be formed successively by a sputtering method without exposure to air.

A mask 122 is formed over the n-type semiconductor film 114 and the conductive film 121, and with use of the mask 122, the conductive film 121 is processed by wet etching to form the source and drain electrode layers 105 a and 105 b (see FIG. 4C).

Next, the n-type semiconductor film 114 is processed by dry etching to form the buffer layers 104 a and 104 b (see FIG. 4D). The semiconductor layer 112 is partly etched in the same step, so that the semiconductor layer 103 is formed. The same mask is used in the etching step for forming the buffer layers 104 a and 104 b and the etching step for forming the source and drain electrode layers 105 a and 105 b as in the case of FIGS. 4C and 4D, whereby the number of masks can be reduced; therefore, simplification of process and reduction in cost can be achieved.

An insulating film may be formed as a protective film over each of the thin film transistors 170 a, 170 b, and 170 c. The protective film can be formed in a manner similar to formation of the gate insulating layer. Note that the protective film is provided to prevent entry of a contaminant impurity such as an organic substance, a metal substance, or moisture floating in air and is preferably a dense film. For example, a stacked layer of a silicon oxide film and a silicon nitride film may be formed as the protective film over each of the thin film transistors 170 a, 170 b, and 170 c.

Further, it is preferable that heat treatment be performed on the oxide semiconductor film such as the semiconductor layer 103 or the buffer layers 104 a and 104 b after film formation. Heat treatment may be performed in any step after film formation step, and it can be performed immediately after film formation, after formation of the conductive film 117, after formation of the protective film, or the like. Further, such heat treatment may be performed to serve as another heat treatment. The heat temperature may be from 300° C. to 400° C. inclusive, preferably, 350° C. In the case where the semiconductor layer 103 and the buffer layers 104 a and 104 b are successively formed as the case of the thin film transistor in FIGS. 2A and 2B, heat treatment may be performed after the layers are stacked. Heat treatment may be performed plural times so that heat treatment of the semiconductor layer 103 and heat treatment of the buffer layers 104 a and 104 b are performed in different steps.

The end portions of the source and drain electrode layers 105 a and 105 b are not aligned with the end portions of the buffer layers 104 a and 104 b, whereby the distance between the end portions of the source and drain electrode layers 105 a and 105 b is long. Therefore, generation of a leakage current and short circuit between the source and drain electrode layers 105 a and 105 b can be prevented. Accordingly, a thin film transistor with high reliability and high withstand voltage can be manufactured.

Alternatively, as the thin film transistor 170 c of FIGS. 2A and 2B, a structure in which the end portions of the buffer layers 104 a and 104 b and the end portions of the source and drain electrode layers 105 a and 105 b are aligned may be formed. Etching for forming the source and drain electrode layers 105 a and 105 b and etching for forming the buffer layers 104 a and 104 b are dry etching, whereby a structure of the thin film transistor 170 c of FIGS. 2A and 2B can be obtained. Alternatively, a structure of the thin film transistor 170 c of FIGS. 2A and 2B can be formed by forming the buffer layers 104 a and 104 b by etching the n-type semiconductor film 115 with use of the source and drain electrode layers 105 a and 105 b as a mask.

In the case of a structure where a gate electrode layer, a gate insulating layer, and a semiconductor layer (an oxide semiconductor layer containing In, Ga, and Zn), and a source and drain electrode layers are stacked without providing a buffer layer (an n-type oxide semiconductor layer containing In, Ga, and Zn), a distance between the gate electrode layer and the source or drain electrode layer is small so that parasitic capacitance generated between the gate electrode layer and the source or drain electrode layer increases. Furthermore, parasitic capacitance is significantly increased by a thin semiconductor layer. In this embodiment, the buffer layer having a high carrier concentration, which is an n-type oxide semiconductor layer containing In, Ga, and Zn is provided, and the thin film transistor has a structure where the gate electrode layer, the gate insulating layer, the semiconductor layer, the buffer layer, and the source and drain electrode layers are stacked. Therefore, parasitic capacitance can be suppressed even if the semiconductor layer has a small thickness.

According to this embodiment, a thin film transistor with small photoelectric current, small parasitic capacitance, and high on-off ratio can be obtained, so that a thin film transistor having excellent dynamic characteristics can be manufactured. Therefore, a semiconductor device including thin film transistors with high electric properties and high reliability can be provided.

Embodiment 2

In this embodiment, an example of a thin film transistor having a multi-gate structure will be described. Accordingly, except the gate structure, the thin film transistor can be formed in a manner similar to Embodiment 1, and repetitive description of the same portions as or portions having functions similar to those in Embodiment 1 and manufacturing steps will be omitted.

In this embodiment, a thin film transistor included in a semiconductor device will be described with reference to FIGS. 5A and 5B, FIGS. 6A and 6B, and FIGS. 7A and 7B.

FIG. 5A is a plan view illustrating a thin film transistor 171 a and FIG. 5B is a cross-sectional view of the thin film transistor 171 a taken along a line E1-E2 of FIG. 5A.

As illustrated in FIGS. 5A and 5B, over a substrate 150, a thin film transistor 171 a having a multi-gate structure, which includes gate electrode layers 151 a and 151 b, a gate insulating layer 152, semiconductor layers 153 a and 153 b, buffer layers 154 a, 154 b, and 154 c, and a source and drain electrode layers 155 a and 155 b, is formed.

The semiconductor layers 153 a and 153 b are oxide semiconductor layers containing In, Ga, and Zn, and the buffer layers 154 a, 154 b, and 154 c are n-type oxide semiconductor layers containing In, Ga, and Zn. The buffer layers 154 a, 154 b, and 154 c functioning as a source and drain regions (n⁺ layers) have higher carrier concentration than the semiconductor layers 153 a and 153 b.

The semiconductor layers 153 a and 153 b are electrically connected to each other with the buffer layer 154 c interposed therebetween. In addition, the semiconductor layer 153 a is electrically connected to the source and drain electrode layer 155 a with the buffer layer 154 a interposed therebetween and the semiconductor layer 153 b is electrically connected to the source and drain electrode layer 155 b with the buffer layer 154 b interposed therebetween.

FIGS. 6A and 6B illustrate a thin film transistor 171 b having another multi-gate structure. FIG. 6A is a plan view of the thin film transistor 171 b and FIG. 6B is a cross-sectional view thereof taken along a line F1-F2 of FIG. 6A. In the thin film transistor 171 b of FIGS. 6A and 6B, a wiring layer 156 which is formed in the same step of formation of the source and drain electrode layers 155 a and 155 b is provided over the buffer layer 154 c, and the semiconductor layers 153 a and 153 b are electrically connected to each other with the buffer layer 154 c and the wiring layer 156 interposed therebetween.

FIGS. 7A and 7B illustrate a thin film transistor 171 c having another multi-gate structure. FIG. 7A is a plan view of the thin film transistor 171 c and FIG. 7B is a cross-sectional view thereof taken along a line G1-G2 of FIG. 7A. In the thin film transistor 171 c of FIGS. 7A and 7B, the semiconductor layers 153 a and 153 b are formed as a continuous semiconductor layer 153. The semiconductor layer 153 is formed so as to extend over the gate electrode layers 151 a and 151 b with the gate insulating layer 152 interposed therebetween.

As described above, in the thin film transistor having a multi-gate structure, the semiconductor layer formed over the gate electrode layers may be provided continuously or a plurality of semiconductor layers which are electrically connected to each other with the buffer layer, the wiring layer, or the like interposed therebetween may be provided.

The thin film transistor having a multi-gate structure of this embodiment has small off current, and a semiconductor device including such a thin film transistor can have high electric properties and high reliability.

In this embodiment, a double-gate structure in which two gate electrode layers are provided is described as an example of a multi-gate structure; however, a triple-gate structure in which a larger number of gate electrode layers are provided can be applied to the present invention.

This embodiment can be combined with any of the other embodiments as appropriate.

Embodiment 3

In this embodiment, an example of a thin film transistor in which a buffer layer has a layered structure will be described. Therefore, except the buffer layer, the thin film transistor can be formed in a manner similar to Embodiment 1 or Embodiment 2, and repetitive description of the same portions as or portions having functions similar to those in Embodiment 1 or Embodiment 2, and manufacturing steps will be omitted.

In this embodiment, a thin film transistor 173 used in a semiconductor device is described with reference to FIG. 8.

As illustrated in FIG. 8, over the substrate 100, the thin film transistor 173 including the gate electrode layer 101, the semiconductor layer 103, buffer layers 106 a and 106 b, the buffer layers 104 a and 104 b, and the source and drain electrode layers 105 a and 105 b is formed.

In the thin film transistor 173 of this embodiment, the buffer layers 106 a and 106 b are provided as a second buffer layer between the semiconductor layer 103 and the buffer layers 104 a and 104 b.

The semiconductor layer 103 is an oxide semiconductor layer containing In, Ga, and Zn, and the buffer layers 104 a and 104 b and the buffer layer 106 a and 106 b are each an n-type oxide semiconductor layer containing In, Ga, and Zn.

The second buffer layer (the buffer layers 106 a and 106 b) provided between the semiconductor layer 103 and the buffer layers 104 a and 104 b has a carrier concentration which is higher than the semiconductor layer 103 but lower than the buffer layers 104 a and 104 b. The buffer layers 104 a and 104 b function as n⁺ layers, and the second buffer layers (the buffer layers 106 a and 106 b) function as n⁻ layers.

In this embodiment, it is preferable that the carrier concentration appropriate for the semiconductor layer 103 be lower than 1×10¹⁷ atoms/cm³ (more preferably, 1×10¹¹ atoms/cm³ or higher) and the carrier concentration appropriate for the buffer layer be 1×10¹⁸ atoms/cm³ or higher (more preferably, 1×10²² atoms/cm³ or lower).

If the carrier concentration range of the semiconductor layer 103 for a channel exceeds the above range, the thin film transistor has a risk of being normally on. Therefore, with use of the IGZO film having the carrier concentration range of this embodiment as a channel of the semiconductor layer 103, a highly reliable thin film transistor can be provided.

The carrier concentration appropriate for the buffer layers 106 a and 106 b functioning as n⁻ layers may be lower than that of the buffer layers 104 a and 104 b functioning as n⁺ layers but higher than that of the semiconductor layer 103.

As described above, the buffer layer provided between the semiconductor layer and the source and drain electrode layers may have a layered structure, and the carrier concentration of the buffer layers is controlled to become higher from the semiconductor layer toward the source and drain electrode layers.

The thin film transistor including the layered buffer layer of this embodiment has small off current, and a semiconductor device including such a thin film transistor can have high electric properties and high reliability.

This embodiment can be combined with any of the other embodiments as appropriate.

Embodiment 4

In this embodiment, an example in which a shape of the thin film transistor and a manufacturing method of the thin film transistor are partly different from those of Embodiment 1. Except the shape, the thin film transistor can be formed in a manner similar to Embodiment 1; thus, repetitive description of the same portions as or portions having functions similar to those in Embodiment 1 and manufacturing steps will be omitted.

In this embodiment, a thin film transistor 174 used in a display device and manufacturing steps thereof will be described with reference to FIGS. 9A and 9B and FIGS. 10A to 10D. FIG. 9A is a plan view of the thin film transistor 174, FIG. 9B is a cross-sectional view thereof taken along a line D1-D2 of FIG. 9A, and FIGS. 10A to 10D are cross-sectional views illustrating manufacturing steps thereof taken along the line D1-D2.

As illustrated in FIGS. 9A and 9B, over the substrate 100, the thin film transistor 174 including the gate electrode layer 101, the semiconductor layer 103, the buffer layers 104 a and 104 b, and the source and drain electrode layers 105 a and 105 b is provided.

The semiconductor layer 103 is an oxide semiconductor layer containing In, Ga, and Zn, and the buffer layers 104 a and 104 b are n-type oxide semiconductor layers containing In, Ga, and Zn. The buffer layers 104 a and 104 b function as a source and drain regions (n⁺ layers) and have higher carrier concentration than the semiconductor layer 103.

The semiconductor layer 103 is electrically connected to the source and drain electrode layers 105 a and 105 b with the buffer layers 104 a and 104 b interposed therebetween, respectively.

Manufacturing steps of the thin film transistor 174 are described with reference to FIGS. 10A to 10D. The gate electrode layer 101 is formed over the substrate 100. Next, over the gate electrode layer 101, the semiconductor film 131 which is an oxide semiconductor film containing In, Ga, and Zn, the n-type semiconductor film 132 which is an n-type oxide semiconductor film containing In, Ga, and Zn, and the conductive film 133 are formed in this order (see FIG. 10A).

The gate insulating layer 102, the semiconductor film 131 which is an oxide semiconductor film containing In, Ga, and Zn, the n-type semiconductor film 132 which is an n-type oxide semiconductor film containing In, Ga, and Zn, and the conductive film 133 can be successively formed without exposure to air. Successive film formation without exposure to air enables each interface between stacked layers to be formed without being contaminated with atmospheric components or impurity elements floating in air. Thus, variations in characteristics of thin film transistor can be reduced.

In this embodiment, an example in which exposure using a high-tone mask is performed for forming a mask 135 is described. A resist is formed in order to form the mask 135. As the resist, a positive type resist or a negative type resist can be used. Here, a positive resist is used.

Next, the resist is irradiated with light with use of a multi-tone mask as a photomask, so that the resist is exposed to the light.

A multi-tone mask can achieve three levels of light exposure to obtain an exposed portion, a half-exposed portion, and an unexposed portion; one-time exposure and development process enables a resist mask with regions of plural thicknesses (typically, two kinds of thicknesses) to be formed. The use of a multi-tone mask allows the number of photomasks to be reduced.

As typical examples of the multi-tone mask, there are a gray-tone mask and a half-tone mask.

A gray-tone mask includes a light-transmitting substrate, and a light-blocking portion and a diffraction grating which are formed thereover. The light transmittance of the light block portion is 0%. The diffraction grating has a light transmit portion in a slit form, a dot form, a mesh form, or the like with intervals less than or equal to the resolution limit of light used for the exposure; thus, the light transmittance can be controlled. The diffraction grating can have regularly-arranged slits, dots, or meshes form, or irregularly-arranged slits, dots, or meshes.

As the light-transmitting substrate, a substrate having a light-transmitting property, such as a quartz substrate, can be used. The light-blocking portion and the diffraction grating can be formed using a light-blocking material such as chromium or chromium oxide, which absorbs light.

When the gray-tone mask is irradiated with light for exposure, a light transmittance of the light-blocking portion is 0% and that of a region where neither the light-blocking portion nor the diffraction grating is provided is 100%. The light transmittance of the diffraction grating can be controlled in a range of 10% to 70%. The control of the light transmission in the diffraction grating can be performed by adjusting the interval of a slit, dot, or mesh of the diffraction grating and the pitch thereof.

A half-tone mask includes a light-transmitting substrate, and a semi-transmissive portion and a light-blocking portion which are formed thereover. The semi-transmissive portion can be formed using MoSiN, MoSi, MoSiO, MoSiON, CrSi, or the like. The light-blocking portion can be formed of a light-blocking material by which light is absorbed, such as chromium or chromium oxide.

When the half-tone mask is irradiated with light for exposure, the light transmittance of the light-blocking portion is 0% and that of a region where neither the light-blocking portion nor the semi-transmissive portion is provided is 100%. Further, the light transmittance of the semi-transmissive portion can be controlled within a range of 10% to 70%. Control of the transmittance of light through the semi-transmissive portion is possible by control of a material of the semi-transmissive portion.

After the exposure to light using the multi-tone mask, development is performed, whereby the mask 135 including regions with different thicknesses can be formed as illustrated in FIG. 10B.

Next, the semiconductor film 131, the n-type semiconductor film 132, and the conductive film 133 are etched with use of the mask 135 to be separated. As a result, a semiconductor film 136, an n-type semiconductor film 137, and a conductive film 138 can be formed (see FIG. 10B).

Next, ashing is performed on the resist mask 135. As a result, an area of the mask is decreased, and the thickness thereof is reduced. At the time of the ashing, the resist of the mask in a region with a small thickness (a region overlapping with part of the gate electrode 101) is removed, and divided masks 139 can be formed (see FIG. 10C).

The conductive film 138 is etched with use of the masks 139 to form the source and drain electrode layers 105 a and 105 b. When the conductive film 138 is subjected to wet etching as described in this embodiment, the conductive film 138 is isotropically etched. Thus, end portions of the source and drain electrode layers 105 a and 105 b are not aligned with end portions of the masks 139 and positioned inwardly. Accordingly, end portions of the n-type semiconductor film 137 and end portions of the semiconductor film 136 are more outwardly projected than the end portions of the source and drain electrode layers 105 a and 105 b. Then, the n-type semiconductor film 137 and the semiconductor film 136 are etched with use of the masks 139 to form the buffer layers 104 a and 104 b and the semiconductor layer 103 (see FIG. 10D). Note that only part of the semiconductor layer 103 is etched to form a semiconductor layer having a groove.

The groove of the semiconductor layer 103 can be formed in the same step of the formation of the buffer layers 104 a and 104 b. At the same time, the end portion of the semiconductor layer 103 is partly etched and exposed. Then, the mask 139 is removed.

Through the above steps, the thin film transistor 174 illustrated in FIGS. 9A and 9B can be manufactured.

The use of a resist mask including regions of plural thicknesses (typically, two kinds of thicknesses) formed with use of a multi-tone mask as in this embodiment enables the number of resist masks to be reduced; therefore, the process can be simplified and cost can be reduced.

This embodiment can be combined with any of the other embodiments as appropriate.

Embodiment 5

In this embodiment, an example will be described below, in which at least part of a driver circuit and a thin film transistor arranged in a pixel portion are formed over the same substrate in a display device which is one example of a semiconductor device of the invention disclosed in this specification.

The thin film transistor to be arranged in the pixel portion is formed according to any one of Embodiments 1 to 4. Further, the thin film transistor described in any one of Embodiments 1 to 4 is an n-channel TFT, and thus a part of a driver circuit that can include an n-channel TFT among driver circuits is formed over the same substrate as the thin film transistor of the pixel portion.

FIG. 12A illustrates an example of a block diagram of an active matrix liquid crystal display device which is an example of a semiconductor device disclosed in this specification. The display device illustrated in FIG. 12A includes, over a substrate 5300, a pixel portion 5301 including a plurality of pixels that are provided with a display element; a scan line driver circuit 5302 that selects a pixel; and a signal line driver circuit 5303 that controls a video signal input to the selected pixel. The pixel portion 5301 is connected to the signal line driver circuit 5303 by a plurality of signal lines S1 to Sm (not illustrated) that extend in a column direction from the signal line driver circuit 5303, and to the scan line driver circuit 5302 by a plurality of scan lines G1 to Gn (not illustrated) that extend in a row direction from the scan line driver circuit 5302. The pixel portion 5301 includes a plurality of pixels (not illustrated) arranged in matrix so as to correspond to the signal lines S1 to Sm and the scan lines G1 to Gn. Each pixel is connected to a signal line Sj (one of the signal lines S1 to Sm) and a scan line Gi (one of the scan lines G1 to Gn).

In addition, the thin film transistor described in any one of Embodiments 1 to 4 is an n-channel TFT, and a signal line driver circuit including the n-channel TFT is described with reference to FIG. 13.

The signal line driver circuit illustrated in FIG. 13 includes a driver IC 5601, switch groups 56021 to 5602_M, a first wiring 5611, a second wiring 5612, a third wiring 5613, and wirings 5621_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M includes a first thin film transistor 5603 a, a second thin film transistor 5603 b, and a third thin film transistor 5603 c.

The driver IC 5601 is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M is connected to the first wiring 5611, the second wiring 5612, and the third wiring 5613, and the wirings 56211 to 5621_M are connected to the switch groups 56021 to 5602_M, respectively. Each of the wirings 5621_1 to 5621_M is connected to three signal lines via the first thin film transistor 5603 a, the second thin film transistor 5603 b, and the third thin film transistor 5603 c. For example, the wiring 5621_J of the J-th column (one of the wirings 5621_1 to 5621_M) is connected to a signal line Sj−1, a signal line Sj, and a signal line Sj+1 via the first thin film transistor 5603 a, the second thin film transistor 5603 b, and the third thin film transistor 5603 c which are includes in the switch group 5602_J.

A signal is input to each of the first wiring 5611, the second wiring 5612, and the third wiring 5613.

Note that the driver IC 5601 is preferably formed over a single crystalline substrate. The switch groups 5602_1 to 5602_M are preferably formed over the same substrate as the pixel portion is. Therefore, the driver IC 5601 and the switch groups 5602_1 to 5602_M are preferably connected through an FPC or the like.

Next, operation of the signal line driver circuit illustrated in FIG. 13 is described with reference to a timing chart in FIG. 14. The timing chart in FIG. 14 illustrates a case where the scan line Gi of the i-th row is selected. A selection period of the scan line Gi of the i-th row is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. In addition, the signal line driver circuit in FIG. 13 operates similarly to that in FIG. 14 even when a scan line of another row is selected.

Note that the timing chart in FIG. 14 shows a case where the wiring 5621_J in the J-th column is connected to the signal line Sj−1, the signal line Sj, and the signal line Sj+1 via the first thin film transistor 5603 a, the second thin film transistor 5603 b, and the third thin film transistor 5603 c.

The timing chart in FIG. 14 shows timing at which the scan line Gi of the i-th row is selected, timing 5703 a of on/off of the first thin film transistor 5603 a, timing 5703 b of on/off of the second thin film transistor 5603 b, timing 5703 c of on/off of the third thin film transistor 5603 c, and a signal 5721_J input to the wiring 5621_J of the J-th column.

In the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, different video signals are input to the wirings 5621_1 to 5621_M. For example, a video signal input to the wiring 5621_J in the first sub-selection period T1 is input to the signal line Sj−1, a video signal input to the wiring 5621_J in the second sub-selection period T2 is input to the signal line Sj, and a video signal input to the wiring 5621_J in the third sub-selection period T3 is input to the signal line Sj+1. In addition, in the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, the video signals input to the wiring 5621_J are denoted by Data_j−1, Data_j, and Data_j+1.

As illustrated in FIG. 14, in the first sub-selection period T1, the first thin film transistor 5603 a is turned on, and the second thin film transistor 5603 b and the third thin film transistor 5603 c are turned off. At this time, Data_j−1 input to the wiring 5621_J is input to the signal line Sj−1 via the first thin film transistor 5603 a. In the second sub-selection period T2, the second thin film transistor 5603 b is turned on, and the first thin film transistor 5603 a and the third thin film transistor 5603 c are turned off. At this time, Data_j input to the wiring 5621_J is input to the signal line Sj via the second thin film transistor 5603 b. In the third sub-selection period T3, the third thin film transistor 5603 c is turned on, and the first thin film transistor 5603 a and the second thin film transistor 5603 b are turned off. At this time, Data_j+1 input to the wiring 5621_J is input to the signal line Sj+1 via the third thin film transistor 5603 c.

As described above, in the signal line driver circuit in FIG. 13, by dividing one gate selection period into three, video signals can be input to three signal lines from one wiring 5621 in one gate selection period. Therefore, in the signal line driver circuit in FIG. 13, the number of connections of the substrate provided with the driver IC 5601 and the substrate provided with the pixel portion can be approximately ⅓ of the number of signal lines. The number of connections is reduced to approximately ⅓ of the number of the signal lines, so that reliability, yield, etc., of the signal line driver circuit in FIG. 13 can be improved.

Note that there are no particular limitations on the arrangement, the number, a driving method, and the like of the thin film transistors, as long as one gate selection period is divided into a plurality of sub-selection periods and video signals are input to a plurality of signal lines from one wiring in the respective sub-selection periods as illustrated in FIG. 13.

For example, when video signals are input to three or more signal lines from one wiring in each of three or more sub-selection periods, it is only necessary to add a thin film transistor and a wiring for controlling the thin film transistor. Note that when one gate selection period is divided into four or more sub-selection periods, one sub-selection period becomes shorter. Therefore, one gate selection period is preferably divided into two or three sub-selection periods.

As another example, one gate selection period may be divided into four periods of a precharge period Tp, the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 as illustrated in a timing chart in FIG. 15. The timing chart in FIG. 15 illustrates timing at which the scan line Gi of the i-th row is selected, timing 5803 a of on/off of the first thin film transistor 5603 a, timing 5803 b of on/off of the second thin film transistor 5603 b, timing 5803 c of on/off of the third thin film transistor 5603 c, and a signal 5821_J input to the wiring 5621_J of the J-th column. As illustrated in FIG. 15, the first thin film transistor 5603 a, the second thin film transistor 5603 b, and the third thin film transistor 5603 c are turned on in the precharge period Tp. At this time, precharge voltage Vp input to the wiring 5621_J is input to each of the signal line Sj−1, the signal line Sj, and the signal line Sj+1 via the first thin film transistor 5603 a, the second thin film transistor 5603 b, and the third thin film transistor 5603 c. In the first sub-selection period T1, the first thin film transistor 5603 a is turned on, and the second thin film transistor 5603 b and the third thin film transistor 5603 c are turned off. At this time, Data_j−1 input to the wiring 5621_J is input to the signal line Sj−1 via the first thin film transistor 5603 a. In the second sub-selection period T2, the second thin film transistor 5603 b is turned on, and the first thin film transistor 5603 a and the third thin film transistor 5603 c are turned off. At this time, Data_j input to the wiring 5621_J is input to the signal line Sj via the second thin film transistor 5603 b. In the third sub-selection period T3, the third thin film transistor 5603 c is turned on, and the first thin film transistor 5603 a and the second thin film transistor 5603 b are turned off. At this time, Data_j+1 input to the wiring 5621_J is input to the signal line Sj+1 via the third thin film transistor 5603 c.

As described above, in the signal line driver circuit in FIG. 13 to which the timing chart in FIG. 15 is applied, the video signal can be written to the pixel at high speed because the signal line can be precharged by providing a precharge selection period before a sub-selection period. Note that portions in FIG. 15 which are similar to those of FIG. 14 are denoted by common reference numerals and detailed description of the portions which are the same and portions which have similar functions is omitted.

Further, a structure of a scan line driver circuit is described. The scan line driver circuit includes a shift register and a buffer. Additionally, the scan line driver circuit may include a level shifter in some cases. In the scan line driver circuit, when the clock signal (CLK) and the start pulse signal (SP) are input to the shift register, a selection signal is produced. The generated selection signal is buffered and amplified by the buffer, and the resulting signal is supplied to a corresponding scan line. Gate electrodes of transistors in pixels of one line are connected to the scan line. Further, since the transistors in the pixels of one line have to be turned on at the same time, a buffer which can feed a large current is used.

One mode of a shift register which is used for a part of a scan line driver circuit is described with reference to FIG. 16 and FIG. 17.

FIG. 16 illustrates a circuit configuration of the shift register. The shift register illustrated in FIG. 16 includes a plurality of flip-flops (flip-flops 5701_1 to 5701_n). The shift register is operated with input of a first clock signal, a second clock signal, a start pulse signal, and a reset signal.

Connection relations of the shift register in FIG. 16 are described. In the i-th stage flip-flop 5701_i (one of the flip-flops 57011 to 5701_n) in the shift register of FIG. 16, a first wiring 5501 illustrated in FIG. 17 is connected to a seventh wiring 5717_i−1; a second wiring 5502 illustrated in FIG. 17 is connected to a seventh wiring 5717_i+1; a third wiring 5503 illustrated in FIG. 17 is connected to a seventh wiring 5717_i; and a sixth wiring 5506 illustrated in FIG. 17 is connected to a fifth wiring 5715.

Further, a fourth wiring 5504 illustrated in FIG. 17 is connected to a second wiring 5712 in flip-flops of odd-numbered stages, and is connected to a third wiring 5713 in flip-flops of even-numbered stages. A fifth wiring 5505 illustrated in FIG. 17 is connected to a fourth wiring 5714.

Note that the first wiring 5501 of the first stage flip-flop 5701_1 illustrated in FIG. 17 is connected to a first wiring 5711. Moreover, the second wiring 5502 of the n-th stage flip-flop 5701_n illustrated in FIG. 17 is connected to a sixth wiring 5716.

Note that the first wiring 5711, the second wiring 5712, the third wiring 5713, and the sixth wiring 5716 may be referred to as a first signal line, a second signal line, a third signal line, and a fourth signal line, respectively. The fourth wiring 5714 and the fifth wiring 5715 may be referred to as a first power supply line and a second power supply line, respectively.

Next, FIG. 17 illustrates details of the flip-flop illustrated in FIG. 16. A flip-flop illustrated in FIG. 17 includes a first thin film transistor 5571, a second thin film transistor 5572, a third thin film transistor 5573, a fourth thin film transistor 5574, a fifth thin film transistor 5575, a sixth thin film transistor 5576, a seventh thin film transistor 5577, and an eighth thin film transistor 5578. Each of the first thin film transistor 5571, the second thin film transistor 5572, the third thin film transistor 5573, the fourth thin film transistor 5574, the fifth thin film transistor 5575, the sixth thin film transistor 5576, the seventh thin film transistor 5577, and the eighth thin film transistor 5578 is an n-channel transistor and is turned on when the gate-source voltage (V_(gs)) exceeds the threshold voltage (V_(th)).

Next, connection structures of the flip-flop illustrated in FIG. 16 are described below.

A first electrode (one of a source electrode and a drain electrode) of the first thin film transistor 5571 is connected to the fourth wiring 5504. A second electrode (the other of the source electrode and the drain electrode) of the first thin film transistor 5571 is connected to the third wiring 5503.

A first electrode of the second thin film transistor 5572 is connected to the sixth wiring 5506. A second electrode of the second thin film transistor 5572 is connected to the third wiring 5503.

A first electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505. A second electrode of the third thin film transistor 5573 is connected to a gate electrode of the second thin film transistor 5572. Agate electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505.

A first electrode of the fourth thin film transistor 5574 is connected to the sixth wiring 5506. A second electrode of the fourth thin film transistor 5574 is connected to the gate electrode of the second thin film transistor 5572. A gate electrode of the fourth thin film transistor 5574 is connected to a gate electrode of the first thin film transistor 5571.

A first electrode of the fifth thin film transistor 5575 is connected to the fifth wiring 5505. A second electrode of the fifth thin film transistor 5575 is connected to the gate electrode of the first thin film transistor 5571. A gate electrode of the fifth thin film transistor 5575 is connected to the first wiring 5501.

A first electrode of the sixth thin film transistor 5576 is connected to the sixth wiring 5506. A second electrode of the sixth thin film transistor 5576 is connected to the gate electrode of the first thin film transistor 5571. A gate electrode of the sixth thin film transistor 5576 is connected to the gate electrode of the second thin film transistor 5572.

A first electrode of the seventh thin film transistor 5577 is connected to the sixth wiring 5506. A second electrode of the seventh thin film transistor 5577 is connected to the gate electrode of the first thin film transistor 5571. A gate electrode of the seventh thin film transistor 5577 is connected to the second wiring 5502. A first electrode of the eighth thin film transistor 5578 is connected to the sixth wiring 5506. A second electrode of the eighth thin film transistor 5578 is connected to the gate electrode of the second thin film transistor 5572. A gate electrode of the eighth thin film transistor 5578 is connected to the first wiring 5501.

Note that the points at which the gate electrode of the first thin film transistor 5571, the gate electrode of the fourth thin film transistor 5574, the second electrode of the fifth thin film transistor 5575, the second electrode of the sixth thin film transistor 5576, and the second electrode of the seventh thin film transistor 5577 are connected are each referred to as a node 5543. The points at which the gate electrode of the second thin film transistor 5572, the second electrode of the third thin film transistor 5573, the second electrode of the fourth thin film transistor 5574, the gate electrode of the sixth thin film transistor 5576, and the second electrode of the eighth thin film transistor 5578 are connected are each referred to as a node 5544.

Note that the first wiring 5501, the second wiring 5502, the third wiring 5503, and the fourth wiring 5504 may be referred to as a first signal line, a second signal line, a third signal line, and a fourth signal line, respectively. The fifth wiring 5505 and the sixth wiring 5506 may be referred to as a first power supply line and a second power supply line, respectively.

In addition, the signal line driver circuit and the scan line driver circuit can be formed using only the n-channel TFTs described in any one of Embodiments 1 to 4. The n-channel TFT described in any one of Embodiments 1 to 4 has a high mobility, and thus a driving frequency of a driver circuit can be increased. Further, parasitic capacitance is reduced by the buffer layer which is an n-type oxide semiconductor layer containing indium, gallium, and zinc; thus the n-channel TFT described in any one of Embodiments 1 to 4 has high frequency characteristics (referred to as f characteristics). For example, a scan line driver circuit using the n-channel TFT described in any one of Embodiments 1 to 4 can operate at high speed, and thus a frame frequency can be increased and insertion of black images can be realized.

In addition, when the channel width of the transistor in the scan line driver circuit is increased or a plurality of scan line driver circuits are provided, for example, higher frame frequency can be realized. When a plurality of scan line driver circuits are provided, a scan line driver circuit for driving even-numbered scan lines is provided on one side and a scan line driver circuit for driving odd-numbered scan lines is provided on the opposite side; thus, increase in frame frequency can be realized.

Further, when an active matrix light-emitting display device which is an example of a semiconductor device disclosed in this specification is manufactured, a plurality of thin film transistors are arranged in at least one pixel, and thus a plurality of scan line driver circuits are preferably arranged. FIG. 12B is a block diagram illustrating an example of an active matrix light-emitting display device.

The light-emitting display device illustrated in FIG. 12B includes, over a substrate 5400, a pixel portion 5401 having a plurality of pixels provided with a display element, a first scan line driver circuit 5402 and a second scan line driver circuit 5404 that select a pixel, and a signal line driver circuit 5403 that controls input of a video signal to the selected pixel.

When the video signal input to a pixel of the light-emitting display device illustrated in FIG. 12B is a digital signal, a pixel emits light or does not emit light by switching of ON/OFF of a transistor. Thus, grayscale can be displayed using an area ratio grayscale method or a time ratio grayscale method. An area ratio grayscale method refers to a driving method by which one pixel is divided into a plurality of subpixels and the respective subpixels are driven independently based on video signals so that grayscale is displayed. Further, a time ratio grayscale method refers to a driving method by which a period during which a pixel is in a light-emitting state is controlled so that grayscale is displayed.

Since the response speed of light-emitting elements is higher than that of liquid crystal elements or the like, the light-emitting elements are more suitable for a time ratio grayscale method than that of liquid-crystal display elements. Specifically, in the case of displaying with a time gray scale method, one frame period is divided into a plurality of subframe periods. Then, in accordance with video signals, the light-emitting element in the pixel is set in a light-emitting state or a non-light-emitting state in each subframe period. By dividing one frame into a plurality of subframes, the total length of time, in which pixels actually emit light in one frame period, can be controlled with video signals so that gray scales are displayed.

In the example of the light-emitting display device illustrated in FIG. 12B, in a case where two TFTs of a switching TFT and a current control TFT are arranged in one pixel, the first scan line driver circuit 5402 generates a signal which is input to a first scan line serving as a gate wiring of the switching TFT, and the second scan line driver circuit 5404 generates a signal which is input to a second scan line serving as a gate wiring of the current control TFT; however, one scan line driver circuit may generate both the signal which is input to the first scan line and the signal which is input to the second scan line. In addition, for example, there is a possibility that a plurality of the first scan lines used for controlling the operation of the switching element are provided in each pixel, depending on the number of transistors included in the switching element. In that case, one scan line driver circuit may generate all signals that are input to the plurality of first scan lines, or a plurality of scan line driver circuits may generate signals that are input to the plurality of first scan lines.

In addition, also in the light-emitting display device, a part of the driver circuit that can include n-channel TFTs among driver circuits can be formed over the same substrate as the thin film transistors of the pixel portion. Alternatively, the signal line driver circuit and the scan line driver circuit can be formed using only the n-channel TFTs described in any one of Embodiments 1 to 4.

Moreover, the above-described driver circuit can be used for electronic paper that drives electronic ink using an element electrically connected to a switching element, without being limited to applications to a liquid crystal display device or a light-emitting display device. The electronic paper is also referred to as an electrophoretic display device (electrophoretic display) and has advantages in that it has the same level of readability as plain paper, it has lower power consumption than other display devices, and it can be made thin and lightweight.

Electrophoretic displays can have various modes. Electrophoretic displays contain a plurality of microcapsules dispersed in a solvent or a solute, each microcapsule containing first particles which are positive-charged and second particles which are negative-charged. By applying an electric field to the microcapsules, the particles in the microcapsules are moved in opposite directions to each other and only the color of the particles concentrated on one side is exhibited. Note that the first particles and the second particles each contain pigment and do not move without an electric field. Moreover, the colors of the first particles and the second particles are different from each other (the colors include colorless or achroma).

In this way, an electrophoretic display is a display that utilizes a so-called dielectrophoretic effect by which a substance that has a high dielectric constant moves to a high-electric field region. An electrophoretic display does not need to use a polarizer and a counter substrate, which are required in a liquid crystal display device, and both the thickness and weight of the electrophoretic display device can be a half of those of a liquid crystal display device.

A solution in which the aforementioned microcapsules are dispersed throughout a solvent is referred to as electronic ink. This electronic ink can be printed on a surface of glass, plastic, cloth, paper, or the like. Furthermore, by use of a color filter or particles that have a pigment, color display is possible, as well.

In addition, if a plurality of the aforementioned microcapsules are arranged as appropriate over an active matrix substrate so as to be interposed between two electrodes, an active matrix display device can be completed, and display can be performed by application of an electric field to the microcapsules. For example, the active matrix substrate obtained by the thin film transistor described in any one of Embodiments 1 to 4 can be used.

Note that the first particles and the second particles in the microcapsules may each be formed of a single material selected from a conductive material, an insulating material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, or a magnetophoretic material or formed of a composite material of any of these.

Through the above steps, a highly reliable display device as a semiconductor device can be manufactured.

This embodiment can be combined with any of the other embodiments as appropriate.

Embodiment 6

In this embodiment, a manufacturing example of an inverted staggered thin film transistor is described, in which at least a gate insulating layer and an oxide semiconductor layer are deposited to be stacked successively without being exposed to air. Here, steps up to the successive deposition are described, and steps after the successive deposition may be carried out in accordance with any of Embodiments 1 to 4 to manufacture a thin film transistor.

In this specification, successive deposition is carried out as follows: a substrate to be processed is placed under an atmosphere which is controlled to be vacuum or an inert gas atmosphere (a nitrogen atmosphere or a rare gas atmosphere) at all times without being exposed to a contaminant atmosphere such as air during a process from a first deposition step using a sputtering method to a second deposition step using a sputtering method. By the successive deposition, deposition can be performed while preventing moisture or the like from being attached again to the substrate to be processed which is cleaned.

Performing the process from the first deposition step to the second deposition step in the same chamber is within the scope of the successive deposition in this specification.

In addition, the following is also within the scope of the successive deposition in this specification: in the case of performing the process from the first deposition step to the second deposition step using plural chambers, the substrate is transferred after the first deposition step to another chamber without being exposed to air and subjected to the second deposition.

Note that between the first deposition step and the second deposition step, a substrate transfer step, an alignment step, a slow-cooling step, a step of heating or cooling the substrate to a temperature which is necessary for the second deposition step, or the like may be provided. Such a process is also within the scope of the successive deposition in this specification.

A step in which liquid is used, such as a cleaning step, wet etching, or formation of a resist may be provided between the first deposition step and the second deposition step. This case is not within the scope of the successive deposition in this specification.

When films are successively deposited without being exposed to air, a multi-chamber manufacturing apparatus as illustrated in FIG. 18 is preferably used.

At the center of the manufacturing apparatus, a transfer chamber 80 equipped with a transfer mechanism (typically, a transfer robot 81) for transferring a substrate is provided. A cassette chamber 82 in which a cassette case storing a plurality of substrates carried into and out of the transfer chamber 80 is set is connected to the transfer chamber 80.

In addition, a plurality of treatment chambers are connected to the transfer chamber 80 through gate valves 84 to 88. In this embodiment, an example in which five treatment chambers are connected to the transfer chamber 80 having a hexagonal top shape is illustrated. Note that, by changing the top shape of the transfer chamber 80, the number of treatment chambers which can be connected to the transfer chamber can be changed. For example, three treatment chambers can be connected to a transfer chamber having a tetragonal shape, or seven treatment chambers can be connected to a transfer chamber having an octagonal shape.

At least one treatment chamber among the five treatment chambers is a sputtering chamber in which sputtering is performed. The sputtering chamber is provided with, at least inside the chamber, a sputtering target, a mechanism for applying electric power or a gas introduction means for sputtering the target, a substrate holder for holding a substrate at a predetermined position, and the like. Further, the sputtering chamber is provided with a pressure control means with which the pressure in the chamber is controlled, so that the pressure is reduced in the sputtering chamber.

Examples of a sputtering method include an RF sputtering method in which a high-frequency power source is used for a sputtering power source, a DC sputtering method, and a pulsed DC sputtering method in which a bias is applied in a pulsed manner. An RF sputtering method is mainly used in the case of depositing an insulating film, and a DC sputtering method is mainly used in the case of depositing a metal film.

In addition, there is also a multi-source sputtering apparatus in which a plurality of targets of different materials can be set. With the multi-source sputtering apparatus, films of different materials can be deposited to be stacked in the same chamber, or a plurality of kinds of materials can be deposited by electric discharge at the same time in the same chamber.

In addition, there are a sputtering apparatus provided with a magnet system inside the chamber and used for a magnetron sputtering method, or a sputtering apparatus used for an ECR sputtering method in which plasma generated with the use of microwaves is used without using glow discharge.

In the sputtering chamber of this embodiment, any of various sputtering methods described above is used as appropriate.

In addition, as a deposition method, there are also a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted with each other during deposition to form a thin compound film thereof, and a bias sputtering method in which voltage is also applied to a substrate during deposition.

In addition, among the five treatment chambers, one of the other treatment chambers than the sputtering chamber is a heating chamber in which a substrate is preheated or the like before sputtering, a cooling chamber in which a substrate is cooled after sputtering, or a chamber in which plasma treatment is performed.

Next, an example of an operation of the manufacturing apparatus is described.

A substrate cassette storing a substrate 94 whose deposition target surface faces downward is set in the cassette chamber 82, and the cassette chamber 82 is placed in a reduced pressure state by a vacuum exhaust means provided in the cassette chamber 82. In each of the treatment chambers and the transfer chamber 80, the pressure is reduced in advance by a vacuum exhaust means provided in each chamber. Accordingly, during transferring the substrate between the treatment chambers, the substrate is not exposed to air and can be kept clean.

Note that at least a gate electrode is provided in advance for the substrate 94 which is placed so that its deposition target surface faces downward. For example, a base insulating film such as a silicon nitride film or a silicon nitride oxide film may also be provided by a plasma CVD method between the substrate and the gate electrode. When a glass substrate containing alkali metal is used as the substrate 94, the base insulating film has an effect of preventing mobile ions of sodium or the like from entering a semiconductor region from the substrate so that variation in electric properties of a TFT can be suppressed.

Here, a substrate over which a silicon nitride film covering the gate electrode is formed by a plasma CVD method to form a first layer of a gate insulating film is used. The silicon nitride film formed by a plasma CVD method is dense, so that generation of pin holes or the like can be suppressed by using this silicon nitride film as the first layer of the gate insulating film. Although this embodiment shows an example in which the gate insulating film has a layered structure, the present invention is not limited thereto, and the gate insulating film may be a single layer or have a layered structure including three or more layers.

Then, the gate valve 83 is opened and the substrate 94 which is the first substrate is picked up from the cassette by the transfer robot 81. After that, the gate valve 84 is opened, the substrate 94 is transferred to a first treatment chamber 89, and then, the gate valve 84 is closed. In the first treatment chamber 89, by heating the substrate 94 by a heater or a lamp, moisture or the like attached to the substrate 94 is removed. In particular, when the gate insulating film contains moisture, a TFT has a risk of changing its electric properties; therefore, heating before sputtering deposition is effective. In the case where moisture has been sufficiently removed at the time when the substrate is set in the cassette chamber 82, this heating treatment is not necessary.

In addition, plasma treatment may be performed on the surface of the first layer of the gate insulating film by providing a plasma treatment means in the first treatment chamber 89. Furthermore, heating for removing moisture may be performed in the cassette chamber 82 by providing a heating means in the cassette chamber 82.

Then, the gate valve 84 is opened and the substrate is transferred to the transfer chamber 80 by the transfer robot 81. After that, the gate valve 85 is opened and the substrate is transferred to a second treatment chamber 90, and the gate valve 85 is closed.

In this embodiment, the second treatment chamber 90 is a sputtering chamber in which sputtering is performed using an RF magnetron sputtering method. In the second treatment chamber 90, a silicon oxide (SiOx) film is deposited as a second layer of the gate insulating film. As the second layer of the gate insulating film, other than a silicon oxide film, an aluminum oxide (Al₂O₃) film, a magnesium oxide (MgOx) film, an aluminum nitride (AlNx) film, an yttrium oxide (YOx) film, or the like can be used.

A small amount of a halogen element such as fluorine or chlorine may be added to the second layer of the gate insulating film so as to immobilize mobile ions of sodium or the like. As a method for adding a small amount of a halogen element, sputtering is performed by introducing a gas containing a halogen element into the chamber. In the case where a gas containing a halogen element is introduced, the exhaust means of the chamber is needed to be provided with an abatement system. The peak of the concentration of a halogen element to be contained in the gate insulating film is measured by secondary ion mass spectrometry (SIMS) and is preferably in the range of from 1×10¹⁵ cm⁻³ to 1×10²⁰ cm⁻³ inclusive.

When the SiOx film is formed, a sputtering method in which artificial quartz is used as a target and a rare gas, typically, argon is used, or a reactive sputtering method in which single crystal silicon is used as a target and chemically reacted with an oxygen gas to obtain a SiOx film can be used. Here, artificial quartz is used as a target, and sputtering is performed in an atmosphere containing only oxygen or an atmosphere containing oxygen of 90% or higher and Ar of 10% or lower so that as much oxygen as possible is contained in a SiOx film. Thus, a SiOx film containing excessive oxygen is formed.

After the SiOx film is deposited, the gate valve 85 is opened, and the substrate is transferred to the transfer chamber 80 by the transfer robot 81 without being exposed to air. Then, the gate valve 86 is opened, the substrate is transferred to a third treatment chamber 91, and the gate valve 86 is closed.

In this embodiment, the third treatment chamber 91 is a sputtering chamber in which sputtering is performed using a DC magnetron sputtering method. In the third treatment chamber 91, an oxide semiconductor film containing In, Ga, and Zn (IGZO film) is deposited as a semiconductor layer. The IGZO film can be deposited using an oxide semiconductor target containing In, Ga, and Zn, in a rare gas atmosphere or an oxygen atmosphere. Here, an oxide semiconductor containing In, Ga, and Zn is used as a target and sputtering is performed by a pulsed DC sputtering method in an atmosphere containing only oxygen or an atmosphere containing oxygen of 90% or higher and Ar of 10% or lower so that as much oxygen as possible is contained in the IGZO film, whereby an IGZO film containing excessive oxygen is formed.

As described above, the SiOx film containing excessive oxygen and the IGZO film containing excessive oxygen are deposited successively without being exposed to air, whereby an interface state between the films containing excessive oxygen can be stabilized, and the reliability of a TFT can be improved. If the substrate is exposed to air before deposition of the IGZO film, moisture or the like is attached and the interface state is adversely affected, which may cause defects such as variation in threshold voltages, deterioration in electric properties, and a normally-on TFT. Moisture is a hydrogen compound. When the films are successively deposited without being exposed to air, the hydrogen compound can be prevented from existing at the interface. Therefore, by successive deposition, variation in threshold voltages can be reduced, deterioration in electric properties can be prevented, or shift of the TFT characteristics to the normally-on side can be reduced, desirably, the shift of the TFT characteristics can be prevented.

In addition, in the second treatment chamber 90 which is a sputtering chamber, both an artificial quartz target and an oxide semiconductor target containing In, Ga, and Zn are placed, and the films are successively deposited by using a shutter; therefore, the films can be stacked in the same chamber. Shutters are provided between the targets and the substrate; one of the shutters is opened for a target which is deposited, and a target which is not deposited is shielded by the other one of the shutters. Advantages of a process in which the films are stacked in the same chamber are the following points: reduction of the number of chambers which are used, and prevention of particles or the like attached to the substrate during transfer of the substrate between different chambers.

Next, the gate valve 86 is opened and the substrate is transferred to the transfer chamber 80 by the transfer robot 81 without being exposed to air.

If a gray-tone mask is not used, the substrate is carried out of the manufacturing apparatus through the cassette chamber at this stage, and the IGZO film containing excessive oxygen is patterned through a photolithography technique. If a gray-tone mask is used, successive deposition described below is performed.

Then, the gate valve 87 is opened, and the substrate is transferred to a fourth treatment chamber 92 without being exposed to air. After that, the gate valve 87 is closed.

In this embodiment, the fourth treatment chamber 92 is a sputtering chamber in which sputtering is performed using a DC magnetron sputtering method. In the fourth treatment chamber 92, sputtering is performed by a pulsed DC sputtering method in an atmosphere containing only a rare gas, so that a second IGZO film that is to be a buffer layer is formed on and in contact with the IGZO film containing excessive oxygen. This second IGZO film has lower oxygen concentration than the IGZO film containing excessive oxygen. Further, the second IGZO film preferably has higher carrier concentration than the IGZO film containing excessive oxygen. As a target, a target in which Mg, Al, or Ti is contained in the oxide semiconductor containing In, Ga, and Zn may be used. Mg, Al, or Ti is a material which easily reacts with oxide, and such a material is contained in the second IGZO film, whereby a blocking effect against oxygen is obtained. Thus, the oxygen concentration in the semiconductor layer can be kept within an optimal range even if heat treatment is performed after deposition. This second IGZO film functions as a source and drain regions.

Next, the gate valve 87 is opened, and the substrate is transferred to the transfer chamber 80 by the transfer robot 81. Then, the gate valve 88 is opened, the substrate is transferred to a fifth treatment chamber 93, and the gate valve 88 is closed. Note that transportation of the substrate is carried out without being exposed to air.

In this embodiment, the fifth treatment chamber 93 is a sputtering chamber in which sputtering is performed using a DC magnetron sputtering method. In the fifth treatment chamber 93, a metal multi-layer film which becomes a source and drain electrode layers is deposited. In the fifth treatment chamber 93 which is a sputtering chamber, both a titanium target and an aluminum target are placed. The films are deposited to be stacked in the same chamber by successive deposition using a shutter. Here, an aluminum film is stacked over a titanium film, and a titanium film is further stacked over the aluminum film.

As described above, when a gray-tone mask is used, the SiOx film containing excessive oxygen, the IGZO film containing excessive oxygen, the second IGZO film, and the metal multi-layer film can be deposited successively without being exposed to air, whereby an interface state of the IGZO film containing excessive oxygen is particularly stabilized, and the reliability of a TFT can be improved. If the substrate is exposed to air before or after deposition of the IGZO film, moisture or the like is attached and the interface state is adversely affected, which may cause defects such as variation in threshold voltages, deterioration in electric properties, and a normally-on TFT. Moisture is a hydrogen compound. When the films are successively deposited without being exposed to air, the hydrogen compound can be prevented from existing at the interface of the IGZO film. Therefore, by successive deposition of the four layers, variation in threshold voltages can be reduced, deterioration in electric properties can be prevented, or shift of the TFT characteristics to the normally-on side can be reduced, desirably, the shift of the TFT characteristics can be prevented.

Further, the second IGZO film that is to be a buffer layer and a metal multi-layer film that is to be a source and drain electrode layers are successively formed without exposure to air, whereby a favorable interface between the second IGZO film and the metal multi-layer film can be formed and contact resistance can be reduced.

Alternatively, an artificial quartz target and an oxide semiconductor target containing In, Ga, and Zn are both placed in the sputtering chamber of the second treatment chamber 90, and three layers are successively formed by shifting gases which are sequentially introduced with use of a shutter, so that the layers can be stacked in the same chamber. Advantages of a process in which the films are stacked in the same chamber are the following points: reduction of the number of chambers which are used, and prevention of particles or the like attached to the substrate during transfer of the substrate between different chambers.

After the above-described steps are repeated to perform a deposition process on a plurality of substrates in a cassette case, the vacuum cassette chamber is exposed to air, and the substrate and the cassette are taken out.

Further, heat treatment, specifically, heat treatment at 300° C. to 400° C., preferably, heat treatment at 350° C. or higher can be performed in the first treatment chamber 89 after deposition of the IGZO film containing excessive oxygen. By such heat treatment, electric properties of an inverted staggered thin film transistor can be improved. Timing of the heat treatment is not limited to a particular timing as long as the heat treatment is performed after deposition of the IGZO film containing excessive oxygen and can be performed right after deposition of the IGZO film containing excessive oxygen or right after deposition of the metal multi-layer film, for example.

Then, each of the stacked films is patterned using a gray-tone mask. The film may be patterned using dry etching or wet etching, or etched by plural times of etching selectively.

Steps after the patterning are carried out in accordance with any one of Embodiments 1 to 4, whereby an inverted staggered thin film transistor can be manufactured.

In this embodiment, a multi-chamber manufacturing apparatus is shown as an example, but an in-line manufacturing apparatus in which sputtering chambers are connected in series may be used and successive deposition may be performed without being exposed to air.

The apparatus illustrated in FIG. 18 has a so-called face-down treatment chamber in which the deposition target surface of the substrate faces downward, but may also have a vertical placement treatment chamber in which a substrate is placed vertically. The vertical placement treatment chamber has an advantage that a footprint is smaller than that of a face-down treatment chamber and can be effectively used in the case where a large-area substrate which could be bent due to its weight is used.

Embodiment 7

A thin film transistor of the invention disclosed in this specification is manufactured, and a semiconductor device having a display function (also referred to as a display device) can be manufactured using the thin film transistor in a pixel portion and further in a driver circuit.

Further, part or whole of a driver circuit can be formed over the same substrate as a pixel portion, using a thin film transistor disclosed in this specification, whereby a system-on-panel can be obtained.

The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light-emitting element (also referred to as a light-emitting display element) can be used. Light-emitting elements include, in its category, an element whose luminance is controlled by current or voltage, and specifically include an inorganic electroluminescent (EL) element, an organic EL element, and the like. Further, a display medium whose contrast is changed by an electric effect, such as an electronic ink, can be used.

In addition, the display device includes a panel in which the display element is sealed, and a module in which an IC including a controller or the like is mounted on the panel. An embodiment of the present invention relates to one mode of an element substrate before the display element is completed in a manufacturing process of the display device, and the element substrate is provided with means for supplying current to the display element in each of a plurality of pixels. Specifically, the element substrate may be in a state provided with only a pixel electrode of the display element, a state after a conductive film to be a pixel electrode is formed and before the conductive film is etched to form the pixel electrode, or any of other states.

Note that a display device in this specification means an image display device, a display device, or a light source (including a lighting device). Further, the display device includes any of the following modules in its category: a module to which a connector such as a flexible printed circuit (FPC), tape automated bonding (TAB) tape, or a tape carrier package (TCP) is attached; a module having TAB tape or a TCP which is provided with a printed wiring board at the end thereof; and a module having an integrated circuit (IC) which is directly mounted on a display element by a chip on glass (COG) method.

In this embodiment, a liquid crystal display device will be described as an example of a semiconductor device of the invention disclosed in this specification.

FIGS. 19A and 19B illustrate an active-matrix liquid crystal display device to which the invention disclosed in this specification is applied. FIG. 19A is a plan view of the liquid crystal display device. FIG. 19B is a cross-sectional view taken along a line V-X of FIG. 19A. A thin film transistor 201 used in the semiconductor device can be manufactured in a manner similar to the thin film transistor described in Embodiment 2 and is a highly reliable thin film transistor including an IGZO semiconductor layer and an n-type IGZO semiconductor layer. The thin film transistor described in Embodiment 1, 3, or 4 can also be used as the thin film transistor 201 of this embodiment.

The liquid crystal display device of this embodiment illustrated in FIG. 19A includes a source wiring layer 202, the inverted staggered thin film transistor 201 with a multi-gate structure, a gate wiring layer 203, and a capacitor wiring layer 204.

Further, in FIG. 19B, in the liquid crystal display device of this embodiment, a substrate 200 provided with the thin film transistor 201 with a multi-gate structure, an insulating layer 211, an insulating layer 212, an insulating layer 213, an electrode layer 255 used for a display element, an insulating layer 261 serving as an alignment film, and a polarizing plate 268 and a substrate 266 provided with an insulating layer 263 serving as an alignment film, an electrode layer 265 used for a display element, a coloring layer 264 serving as a color filter, and a polarizing plate 267 face to each other with a liquid crystal layer 262 interposed therebetween; thus, a liquid crystal display element 260 is formed.

Alternatively, liquid crystal showing a blue phase for which an alignment film is unnecessary may be used. A blue phase is one of liquid crystal phases, which is generated just before a cholesteric phase changes into an isotropic phase while temperature of cholesteric liquid crystal is increased. Since the blue phase is generated within an only narrow range of temperature, liquid crystal composition containing a chiral agent at 5 wt % so as to improve the temperature range is used for the liquid crystal layer 262. The liquid crystal composition which includes liquid crystal showing a blue phase and a chiral agent have such characteristics that the response time is 10 μs to 100 μs, which is small, the alignment process is unnecessary because the liquid crystal composition has optical isotropy, and viewing angle dependency is small.

Although FIGS. 19A and 19B illustrate an example of a transmissive liquid crystal display device, an embodiment of the present invention can also be applied to a reflective liquid crystal display device and a transflective liquid crystal display device.

While FIGS. 19A and 19B illustrate an example of the liquid crystal display device in which the polarizing plate 267 is provided in a position outer than the substrate 266 (on the viewer side) and the coloring layer 264 and the electrode layer 265 used for a display element are provided in a position inner than the substrate 266 in that order, the polarizing plate 267 may be provided in an inner position than the substrate 266. The stacked structure of the polarizing plate and the coloring layer is not limited to that shown in FIG. 19B and may be set as appropriate depending on materials of the polarizing plate and the coloring layer or conditions of manufacturing steps. Further, a light-blocking film serving as a black matrix may be provided.

In this embodiment, in order to reduce surface unevenness of the thin film transistor and to improve reliability of the thin film transistor, the thin film transistor obtained by Embodiment 1 is covered with the insulating layers (the insulating layer 211, the insulating layer 212, and the insulating layer 213) functioning as a protective film or a planarizing insulating film. Note that the protective film is provided to prevent entry of contaminant impurities such as an organic substance, a metal substance, or moisture floating in air and is preferably a dense film. The protective film may be formed with a single layer or a stacked layer of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and/or a silicon nitride oxide film. Alternatively, as the protective film, a silicon oxide film may be formed using a process gas containing an organosilane gas and oxygen by a plasma CVD method.

As examples of organosilane, the following compounds can be given: tetraethoxysilane (TEOS) (chemical formula: Si(OC₂H₅)₄), tetramethylsilane (TMS) (chemical formula: Si(CH₃)₄), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (chemical formula: SiH(OC₂H₅)₃), trisdimethylaminosilane (chemical formula: SiH(N(CH₃)₂)₃), and the like.

As a first layer of the protective film, the insulating layer 211 is formed. The insulating layer 211 has an effect of preventing hillock of an aluminum film. Here, as the insulating layer 211, a silicon oxide film is formed by a plasma CVD method. For a process gas for forming the silicon oxide film, TEOS and O₂ are used. The flow rates of TEOS and O₂ are 15 (sccm) and 750 (sccm), respectively. The substrate temperature in the formation step is 300° C.

As a second layer of the protective film, the insulating layer 212 is formed. Here, as the insulating layer 212, a silicon nitride film is formed by a plasma CVD method. For a process gas for forming the silicon nitride film, SiH₄, N₂, NH₃, and H₂ are used. The use of the silicon nitride film as one layer of the protective film can prevent mobile ions of sodium or the like from entering a semiconductor region so that variation in electric properties of the TFT can be suppressed.

After the protective film is formed, the IGZO semiconductor layer may be annealed at 300° C. to 400° C.

The insulating layer 213 is formed as the planarizing insulating film is formed. As the insulating layer 213, an organic material having heat resistance such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy can be used. Other than such organic materials, it is also possible to use a low-dielectric constant material (a low-k material), a siloxane-based resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), or the like. A siloxane-based resin may include as a substituent at least one of fluorine, an alkyl group, and an aryl group, as well as hydrogen. Note that the insulating layer 213 may be formed by stacking a plurality of insulating films formed of these materials.

Note that a siloxane-based resin is a resin formed from a siloxane-based material as a starting material and having the bond of Si—O—Si. The siloxane-based resin may include as a substituent at least one of fluorine, an alkyl group, and aromatic hydrocarbon, as well as hydrogen.

For the formation of the insulating layer 213, the following method can be employed depending on the material: a CVD method, a sputtering method, an SOG method, a spin coating method, a dipping method, a spray application method, a droplet discharge method (e.g., an ink-jet method, screen printing, offset printing, or the like), a doctor knife, a roll coater, a curtain coater, a knife coater, or the like. In the case of forming the insulating layer 213 using a material solution, annealing (300° C. to 400° C.) of the IGZO semiconductor layer may be performed at the same time of a baking step. The baking step of the insulating layer 213 also serves as annealing of the IGZO semiconductor layer, whereby a semiconductor device can be manufactured efficiently.

The electrode layers 255 and 265 each serving as a pixel electrode layer can be formed using a light-transmitting conductive material such as indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide to which silicon oxide is added, or the like.

A conductive composition including a conductive high molecule (also referred to as a conductive polymer) can be used for the electrode layers 255 and 265. The pixel electrode formed using the conductive composition preferably has a sheet resistance of less than or equal to 10000 ohms per square and a transmittance of greater than or equal to 70% at a wavelength of 550 nm. Further, the resistivity of the conductive high molecule included in the conductive composition is preferably less than or equal to 0.1 Ω·cm.

As the conductive high molecule, a so-called n-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of two or more kinds of them, and the like can be given

Through the above process, a highly reliable liquid crystal display device as a semiconductor device can be manufactured.

This embodiment can be combined with any of the other embodiments as appropriate.

Embodiment 8

In this embodiment, an example of electronic paper will be described as a semiconductor device of the invention disclosed in this specification.

FIG. 26 illustrates active matrix electronic paper as an example of a semiconductor device to which the invention disclosed in this specification is applied.

A thin film transistor 581 used for the semiconductor device can be manufactured in a manner similar to the thin film transistor described in Embodiment 2 and is a highly reliable thin film transistor including an IGZO semiconductor layer and an n-type IGZO semiconductor layer. The thin film transistors described in Embodiments 1, 3, or 4 can also be used as the thin film transistor 581 of this embodiment.

The electronic paper in FIG. 26 is an example of a display device using a twisting ball display system. The twisting ball display system refers to a method in which spherical particles each colored in black and white are arranged between a first electrode layer and a second electrode layer which are electrode layers used for a display element, and a potential difference is generated between the first electrode layer and the second electrode layer to control orientation of the spherical particles, so that display is performed.

The thin film transistor 581 over a substrate 580 is an inverted staggered thin film transistor with a multi-gate structure, and a source or drain electrode layer thereof is in contact with a first electrode layer 587 through an opening formed in insulating layers 583, 584 and 585, whereby the thin film transistor 581 is electrically connected to the first electrode layer 587. Between the first electrode layer 587 and a second electrode layer 588 provided for a substrate 596, spherical particles 589 each having a black region 590 a, a white region 590 b, and a cavity 594 around the regions which is filled with liquid are provided. A space around the spherical particles 589 is filled with a filler 595 such as a resin (see FIG. 26).

Further, instead of the twisting ball, an electrophoretic element can also be used. A microcapsule having a diameter of about 10 m to 200 μm in which transparent liquid, positively charged white microparticles, and negatively charged black microparticles are encapsulated, is used. In the microcapsule which is provided between the first electrode layer and the second electrode layer, when an electric field is applied by the first electrode layer and the second electrode layer, the white microparticles and black microparticles move to opposite sides, so that white or black can be displayed. A display element using this principle is an electrophoretic display element and is called electronic paper in general. The electrophoretic display element has higher reflectance than a liquid crystal display element, and thus, an auxiliary light is unnecessary, power consumption is low, and a display portion can be recognized in a dim place. In addition, even when power is not supplied to the display portion, an image which has been displayed once can be maintained. Accordingly, a displayed image can be stored even if a semiconductor device having a display function (which may be referred to simply as a display device or a semiconductor device provided with a display device) is distanced from an electric wave source.

Through the above process, highly reliable electronic paper as a semiconductor device can be manufactured.

This embodiment can be combined with any of the other embodiments as appropriate.

Embodiment 9

In this embodiment, an example of a light-emitting display device will be described as a semiconductor device of the invention disclosed in this specification. As a display element included in a display device, a light-emitting element utilizing electroluminescence is described here. Light-emitting elements utilizing electroluminescence are classified according to whether a light-emitting material is an organic compound or an inorganic compound. In general, the former is referred to as an organic EL element, and the latter is referred to as an inorganic EL element.

In an organic EL element, by application of voltage to a light-emitting element, electrons and holes are separately injected from a pair of electrodes into a layer containing a light-emitting organic compound, and current flows. The carriers (electrons and holes) are recombined, and thus, the light-emitting organic compound is excited. The light-emitting organic compound returns to a ground state from the excited state, thereby emitting light. Owing to such a mechanism, this light-emitting element is referred to as a current-excitation light-emitting element.

The inorganic EL elements are classified according to their element structures into a dispersion-type inorganic EL element and a thin-film inorganic EL element. A dispersion-type inorganic EL element has a light-emitting layer where particles of a light-emitting material are dispersed in a binder, and its light emission mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. A thin-film inorganic EL element has a structure where a light-emitting layer is sandwiched between dielectric layers, which are further sandwiched between electrodes, and its light emission mechanism is localized type light emission that utilizes inner-shell electron transition of metal ions. Note that description is made here using an organic EL element as a light-emitting element.

FIGS. 22A and 22B illustrate an active-matrix light-emitting display device as an example of a semiconductor device to which the invention disclosed in this specification is applied. FIG. 22A is a plan view of the light-emitting display device, and FIG. 22B is a cross-sectional view taken along a line Y-Z of FIG. 22A. FIG. 23 illustrates an equivalent circuit of the light-emitting display device illustrated in FIGS. 22A and 22B.

Thin film transistors 301 and 302 used for a semiconductor device can be manufactured in a manner similar to any of the thin film transistors described in Embodiments 1 and 2 and are highly reliable thin film transistors each including an IGZO semiconductor layer and an n-type IGZO semiconductor layer. The thin film transistor described in Embodiment 3 or 4 can also be used as the thin film transistors 301 and 302 of this embodiment.

The light-emitting display device of this embodiment illustrated in FIG. 22A and FIG. 23 includes the thin film transistor 301 with a multi-gate structure, the thin film transistor 302, a light-emitting element 303, a capacitor element 304, a source wiring layer 305, a gate wiring layer 306, and a power supply line 307. The thin film transistors 301 and 302 are n-channel thin film transistors.

In FIG. 22B, the light-emitting display device of this embodiment includes, over a substrate 300, the thin film transistor 302; an insulating layer 311; an insulating layer 312; an insulating layer 313; a partition wall 321; and a first electrode layer 320, an electroluminescent layer 322, and a second electrode layer 323 which are used for the light-emitting element 303.

The insulating layer 313 is preferably formed using an organic resin such as acrylic, polyimide, or polyamide or using siloxane.

Since the thin film transistor 302 in the pixel is an n-channel transistor in this embodiment, the first electrode layer 320 which is a pixel electrode layer is desirably a cathode. Specifically, for the cathode, a material with a low work function such as Ca, Al, CaF, MgAg, or AlLi can be used.

The partition wall 321 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. It is particularly preferable that the partition wall 321 be formed using a photosensitive material and an opening be formed over the first electrode layer 320 so that a sidewall of the opening is formed as an inclined surface with continuous curvature.

The electroluminescent layer 322 may be formed with a single layer or a plurality of layers stacked.

The second electrode layer 323 as an anode is formed to cover the electroluminescent layer 322. The second electrode layer 323 can be formed using a light-transmitting conductive film using any of the light-transmitting conductive materials listed in Embodiment 7 for the pixel electrode layer. The second electrode layer 323 may also be formed using a titanium nitride film or a titanium film instead of the above-described light-transmitting conductive film. The light-emitting element 303 is formed by overlapping of the first electrode layer 320, the electroluminescent layer 322, and the second electrode layer 323. After that, a protective film may be formed over the second electrode layer 323 and the partition wall 321 in order to prevent entry of oxygen, hydrogen, moisture, carbon dioxide, or the like into the light-emitting element 303. As the protective film, a silicon nitride film, a silicon nitride oxide film, a DLC film, or the like can be formed.

Further, in a practical case, it is preferable that a display device completed to the state illustrated in FIG. 22B be packaged (sealed) with a protective film (such as a laminate film or an ultraviolet curable resin film) or a cover material with high air-tightness and little degasification so that the display device is not exposed to the outside air.

Next, structures of the light-emitting element will be described with reference to FIGS. 24A to 24C. Across-sectional structure of a pixel will be described by taking an n-channel driving TFT as an example. Driving TFTs 7001, 7011, and 7021 used for semiconductor devices illustrated in FIGS. 24A to 24C can be manufactured in a manner similar to the thin film transistor described in Embodiment 1 and are highly reliable thin film transistors each including an IGZO semiconductor layer and an n-type IGZO semiconductor layer. Alternatively, the thin film transistor described in Embodiments 2, 3, or 4 can be employed as the driving TFTs 7001, 7011, and 7021.

In order to extract light emitted from the light-emitting element, at least one of the anode and the cathode is required to transmit light. A thin film transistor and a light-emitting element are formed over a substrate. A light-emitting element can have a top emission structure, in which light emission is extracted through the surface opposite to the substrate; a bottom emission structure, in which light emission is extracted through the surface on the substrate side; or a dual emission structure, in which light emission is extracted through the surface opposite to the substrate and the surface on the substrate side. The pixel structure of this embodiment can be applied to a light-emitting element having any of these emission structures.

A light-emitting element having a top emission structure will be described with reference to FIG. 24A.

FIG. 24A is a cross-sectional view of a pixel in the case where the driving TFT 7001 is an n-channel TFT and light is emitted from a light-emitting element 7002 to an anode 7005 side. In FIG. 24A, a cathode 7003 of the light-emitting element 7002 is electrically connected to the driving TFT 7001, and a light-emitting layer 7004 and the anode 7005 are stacked in this order over the cathode 7003. The cathode 7003 can be formed using a variety of conductive materials as long as they have a low work function and reflect light. For example, Ca, Al, CaF, MgAg, AlLi, or the like is preferably used. The light-emitting layer 7004 may be formed using a single layer or a plurality of layers stacked. When the light-emitting layer 7004 is formed using a plurality of layers, the light-emitting layer 7004 is formed by stacking an electron-injecting layer, an electron-transporting layer, a light-emitting layer, a hole-transporting layer, and a hole-injecting layer in this order over the cathode 7003. It is not necessary to form all of these layers. The anode 7005 is formed using a light-transmitting conductive film such as a film of indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added.

The light-emitting element 7002 corresponds to a region where the cathode 7003 and the anode 7005 sandwich the light-emitting layer 7004. In the case of the pixel illustrated in FIG. 24A, light is emitted from the light-emitting element 7002 to the anode 7005 side as indicated by an arrow.

Next, a light-emitting element having a bottom emission structure will be described with reference to FIG. 24B. FIG. 24B is a cross-sectional view of a pixel in the case where the driving TFT 7011 is an n-channel transistor and light is emitted from a light-emitting element 7012 to a cathode 7013 side. In FIG. 24B, the cathode 7013 of the light-emitting element 7012 is formed over a light-transmitting conductive film 7017 that is electrically connected to the driving TFT 7011, and a light-emitting layer 7014 and an anode 7015 are stacked in this order over the cathode 7013. A light-blocking film 7016 for reflecting or blocking light may be formed to cover the anode 7015 when the anode 7015 has a light-transmitting property. For the cathode 7013, a variety of materials can be used as in the case of FIG. 24A as long as they are conductive materials having a low work function. The cathode 7013 is formed to have a thickness that can transmit light (preferably, approximately 5 nm to 30 nm). For example, an aluminum film with a thickness of 20 nm can be used as the cathode 7013. Similar to the case of FIG. 24A, the light-emitting layer 7014 may be formed using either a single layer or a plurality of layers stacked. The anode 7015 is not required to transmit light, but can be formed using a light-transmitting conductive material as in the case of FIG. 24A. As the light-blocking film 7016, a metal or the like that reflects light can be used for example; however, it is not limited to a metal film. For example, a resin or the like to which black pigments are added can also be used.

The light-emitting element 7012 corresponds to a region where the cathode 7013 and the anode 7015 sandwich the light-emitting layer 7014. In the case of the pixel illustrated in FIG. 24B, light is emitted from the light-emitting element 7012 to the cathode 7013 side as indicated by an arrow.

Next, a light-emitting element having a dual emission structure will be described with reference to FIG. 24C. In FIG. 24C, a cathode 7023 of a light-emitting element 7022 is formed over a light-transmitting conductive film 7027 which is electrically connected to the driving TFT 7021, and a light-emitting layer 7024 and an anode 7025 are stacked in this order over the cathode 7023. As in the case of FIG. 24A, the cathode 7023 can be formed using a variety of conductive materials as long as they have a low work function. The cathode 7023 is formed to have a thickness that can transmit light. For example, a film of Al having a thickness of 20 nm can be used as the cathode 7023. As in FIG. 24A, the light-emitting layer 7024 may be formed using either a single layer or a plurality of layers stacked. The anode 7025 can be formed using a light-transmitting conductive material as in the case of FIG. 24A.

The light-emitting element 7022 corresponds to a region where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap with one another. In the case of the pixel illustrated in FIG. 24C, light is emitted from the light-emitting element 7022 to both the anode 7025 side and the cathode 7023 side as indicated by arrows.

Note that, although an organic EL element is described here as a light-emitting element, an inorganic EL element can also be provided as a light-emitting element.

In this embodiment, the example is described in which a thin film transistor (a driving TFT) which controls the driving of a light-emitting element is electrically connected to the light-emitting element; however, a structure may be employed in which a TFT for current control is connected between the driving TFT and the light-emitting element.

A semiconductor device described in this embodiment is not limited to the structures illustrated in FIGS. 24A to 24C and can be modified in various ways based on the spirit of techniques according to the invention disclosed in this specification.

Through the above process, a highly reliable light-emitting display device as a semiconductor device can be manufactured.

This embodiment can be combined with any of the other embodiments as appropriate.

Embodiment 10

Next, a structure of a display panel, which is an embodiment of the semiconductor device of the present invention, will be described below. In this embodiment, a liquid crystal display panel (also referred to as a liquid crystal panel), which is one embodiment of a liquid crystal display device having a liquid crystal element as a display element, and a light-emitting display panel (also referred to as a light-emitting panel), which is one embodiment of a semiconductor device having a light-emitting element as a display element, will be described.

Next, the appearance and a cross section of a light-emitting display panel, which is one embodiment of the semiconductor device of the invention disclosed in this specification, will be described with reference to FIGS. 25A and 25B. FIG. 25A is a top view of a panel in which a highly reliable thin film transistor including an IGZO semiconductor layer and an n-type IGZO semiconductor layer and a light-emitting element are sealed between a first substrate and a second substrate with a sealant. FIG. 25B is a cross-sectional view taken along a line H-I of FIG. 25A.

A sealant 4505 is provided so as to surround a pixel portion 4502, signal line driver circuits 4503 a and 4503 b, and scan line driver circuits 4504 a and 4504 b which are provided over a first substrate 4501. In addition, a second substrate 4506 is provided over the pixel portion 4502, the signal line driver circuits 4503 a and 4503 b, and the scan line driver circuits 4504 a and 4504 b. Accordingly, the pixel portion 4502, the signal line driver circuits 4503 a and 4503 b, and the scan line driver circuits 4504 a and 4504 b are sealed together with a filler 4507, by the first substrate 4501, the sealant 4505, and the second substrate 4506.

The pixel portion 4502, the signal line driver circuits 4503 a and 4503 b, and the scan line driver circuits 4504 a and 4504 b formed over the first substrate 4501 each include a plurality of thin film transistors, and a thin film transistor 4510 included in the pixel portion 4502 and a thin film transistor 4509 included in the signal line driver circuit 4503 a are illustrated as an example in FIG. 25B.

Each of the thin film transistors 4509 and 4510 corresponds to a thin film transistor including an IGZO semiconductor layer and an n-type IGZO semiconductor layer, and the thin film transistor described in any one of Embodiments 1 to 4 can be applied thereto. In this embodiment, the thin film transistors 4509 and 4510 are n-channel thin film transistors.

Moreover, reference numeral 4511 denotes a light-emitting element. A first electrode layer 4517 which is a pixel electrode included in the light-emitting element 4511 is electrically connected to a source electrode layer or a drain electrode layer of the thin film transistor 4510. Note that a structure of the light-emitting element 4511 is not limited to that described in this embodiment. The structure of the light-emitting element 4511 can be changed as appropriate depending on the direction in which light is extracted from the light-emitting element 4511, or the like.

In addition, a variety of signals and a potential are supplied to the signal line driver circuits 4503 a and 4503 b, the scan line driver circuits 4504 a and 4504 b, or the pixel portion 4502 from FPCs 4518 a and 4518 b.

In this embodiment, a connection terminal 4515 is formed from the same conductive film as a second electrode layer 4512, and a wiring 4516 is formed using the same conductive film as the first electrode layer 4517 included in the light-emitting element 4511.

The connection terminal 4515 is electrically connected to a terminal included in the FPC 4518 a through an anisotropic conductive film 4519.

A substrate located in the direction in which light is extracted from the light-emitting element 4511 needs to have a light-transmitting property. In that case, a light-transmitting material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

As the filler 4507, an ultraviolet curable resin or a thermosetting resin can be used, in addition to an inert gas such as nitrogen or argon. For example, PVC (polyvinyl chloride), acrylic, polyimide, an epoxy resin, a silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used for the filler 4507.

In addition, if needed, an optical film, such as a polarizing plate, a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate (a quarter-wave plate or a half-wave plate), or a color filter, may be provided as appropriate on a light-emitting surface of the light-emitting element. Further, the polarizing plate or the circularly polarizing plate may be provided with an anti-reflection film. For example, anti-glare treatment by which reflected light can be diffused by projections and depressions on the surface so as to reduce the glare can be performed.

The signal line driver circuits 4503 a and 4503 b and the scan line driver circuits 4504 a and 4504 b may be provided as driver circuits formed using a single crystal semiconductor film or a polycrystalline semiconductor film over a substrate separately prepared. In addition, only the signal line driver circuits or part thereof, or the scan line driver circuits or part thereof may be separately formed and mounted. This embodiment is not limited to the structure illustrated in FIGS. 25A and 25B.

Next, the appearance and a cross section of a liquid crystal display panel, which is one embodiment of the semiconductor device of the invention disclosed in this specification, will be described with reference to FIGS. 20A to 20C. FIGS. 20A and 20B are top views of a panel in which highly reliable thin film transistors 4010 and 4011 each including an IGZO semiconductor layer and an n-type IGZO semiconductor layer, and a liquid crystal element 4013 are sealed between a first substrate 4001 and a second substrate 4006 with a sealant 4005. FIG. 20C is a cross-sectional view taken along a line M-N of FIGS. 20A and 20B.

The sealant 4005 is provided so as to surround a pixel portion 4002 and a scan line driver circuit 4004 which are provided over the first substrate 4001. The second substrate 4006 is provided over the pixel portion 4002 and the scan line driver circuit 4004. Therefore, the pixel portion 4002 and the scan line driver circuit 4004 are sealed together with a liquid crystal layer 4008, by the first substrate 4001, the sealant 4005, and the second substrate 4006. A signal line driver circuit 4003 that is formed using a single crystal semiconductor film or a polycrystalline semiconductor film over a substrate separately prepared is mounted in a region that is different from the region surrounded by the sealant 4005 over the first substrate 4001.

Note that the connection method of a driver circuit which is separately formed is not particularly limited, and a COG method, a wire bonding method, a TAB method, or the like can be used. FIG. 20A illustrates an example of mounting the signal line driver circuit 4003 by a COG method, and FIG. 20B illustrates an example of mounting the signal line driver circuit 4003 by a TAB method.

The pixel portion 4002 and the scan line driver circuit 4004 provided over the first substrate 4001 include a plurality of thin film transistors. FIG. 20C illustrates the thin film transistor 4010 included in the pixel portion 4002 and the thin film transistor 4011 included in the scan line driver circuit 4004.

Each of the thin film transistors 4010 and 4011 corresponds to a thin film transistor including an IGZO semiconductor layer and an n-type IGZO semiconductor layer, and the thin film transistor described in any one of Embodiments 1 to 4 can be employed as the thin film transistors 4010 and 4011. In this embodiment, the thin film transistors 4010 and 4011 are n-channel thin film transistors.

A pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. A counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. A portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap with one another corresponds to the liquid crystal element 4013. Note that the pixel electrode layer 4030 and the counter electrode layer 4031 are provided with an insulating layer 4032 and an insulating layer 4033 respectively which each function as an alignment film, and sandwich the liquid crystal layer 4008 with the insulating layers 4032 and 4033 interposed between the pixel electrode layer 4030 and the counter electrode layer 4031.

Note that the first substrate 4001 and the second substrate 4006 can be formed by using glass, metal (typically, stainless steel), ceramic, or plastic. As plastic, a fiberglass-reinforced plastics (FRP) plate, a polyvinyl fluoride (PVF) film, a polyester film, or an acrylic resin film can be used. In addition, a sheet with a structure in which an aluminum foil is sandwiched between PVF films or polyester films can be used.

Reference numeral 4035 denotes a columnar spacer obtained by selectively etching an insulating film and is provided to control the distance between the pixel electrode layer 4030 and the counter electrode layer 4031 (a cell gap). Further, a spherical spacer may also be used.

Further, a variety of signals and a potential are supplied to the signal line driver circuit 4003 which is formed separately, the scan line driver circuit 4004, or the pixel portion 4002 from an FPC 4018.

In this embodiment, a connection terminal 4015 is formed from the same conductive film as that of the pixel electrode layer 4030 included in the liquid crystal element 4013, and a wiring 4016 is formed from the same conductive film as that of gate electrode layers of the thin film transistors 4010 and 4011.

The connection terminal 4015 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive film 4019.

Note that FIGS. 20A to 20C illustrate an example in which the signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001; however, this embodiment is not limited to this structure. The scan line driver circuit may be separately formed and then mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted.

FIG. 21 illustrates an example in which a liquid crystal display module is formed as a semiconductor device by using a TFT substrate 2600 manufactured according to the invention disclosed in this specification.

FIG. 21 illustrates an example of a liquid crystal display module, in which the TFT substrate 2600 and a counter substrate 2601 are fixed to each other with a sealant 2602, and a pixel portion 2603 including a TFT or the like, a display element 2604 including a liquid crystal layer, and a coloring layer 2605 are provided between the substrates to form a display region. The coloring layer 2605 is necessary to perform color display. In the case of the RGB system, respective coloring layers corresponding to colors of red, green, and blue are provided for respective pixels. Polarizing plates 2606 and 2607 and a diffusion plate 2613 are provided outside the TFT substrate 2600 and the counter substrate 2601. Alight source includes a cold cathode tube 2610 and a reflective plate 2611, and a circuit substrate 2612 is connected to a wiring circuit portion 2608 of the TFT substrate 2600 through a flexible wiring board 2609 and includes an external circuit such as a control circuit or a power source circuit. The polarizing plate and the liquid crystal layer may be stacked with a retardation plate interposed therebetween.

For the liquid crystal display module, a TN (twisted nematic) mode, an IPS (in-plane-switching) mode, an FFS (fringe field switching) mode, an MVA (multi-domain vertical alignment) mode, a PVA (patterned vertical alignment) mode, an ASM (axially symmetric aligned micro-cell) mode, an OCB (optical compensated birefringence) mode, an FLC (ferroelectric liquid crystal) mode, an AFLC (antiferroelectric liquid crystal) mode, or the like can be used.

Through the above process, a highly reliable display panel as a semiconductor device can be manufactured.

This embodiment can be combined with any of the other embodiments as appropriate.

Embodiment 11

A semiconductor device of the invention disclosed in this specification can be applied to electronic paper. Electronic paper can be used for electronic appliances of a variety of fields as long as they can display data. For example, electronic paper can be applied to an electronic book (e-book) reader, a poster, an advertisement in a vehicle such as a train, displays of various cards such as a credit card, and the like. Examples of the electronic appliances are illustrated in FIGS. 28A and 28B and FIG. 29.

FIG. 28A illustrates a poster 2631 formed using electronic paper. In the case where an advertising medium is printed paper, the advertisement is replaced by manpower; however, by using electronic paper to which the invention disclosed in this specification is applied, the advertising display can be changed in a short time. Further, an image can be stably displayed without being distorted. Note that the poster may transmit and receive data wirelessly.

FIG. 28B illustrates an advertisement 2632 in a vehicle such as a train. In the case where an advertising medium is printed paper, the advertisement is replaced by manpower; however, by using electronic paper to which the invention disclosed in this specification is applied, the advertising display can be changed in a short time without a lot of manpower. Further, an image can be stably displayed without being distorted. Note that the advertisement in a vehicle may transmit and receive data wirelessly.

FIG. 29 illustrates an example of an electronic book reader 2700. For example, the electronic book reader 2700 includes two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are combined with a hinge 2711 so that the electronic book reader 2700 can be opened and closed with the hinge 2711 as an axis. With such a structure, the electronic book reader 2700 can be operated like a paper book.

A display portion 2705 and a display portion 2707 are incorporated in the housing 2701 and the housing 2703, respectively. The display portion 2705 and the display portion 2707 may display one image or different images. In the case where the display portion 2705 and the display portion 2707 display different images, for example, a display portion on the right side (the display portion 2705 in FIG. 29) can display text and a display portion on the left side (the display portion 2707 in FIG. 29) can display graphics.

FIG. 29 illustrates an example in which the housing 2701 is provided with an operation portion and the like. For example, the housing 2701 is provided with a power switch 2721, an operation key 2723, a speaker 2725, and the like. With the operation key 2723, pages can be turned. Note that a keyboard, a pointing device, or the like may be provided on the surface of the housing, on which the display portion is provided. Further, an external connection terminal (an earphone terminal, a USB terminal, a terminal that can be connected to various cables such as an AC adapter and a USB cable, or the like), a recording medium insert portion, and the like may be provided on the back surface or the side surface of the housing. Further, the electronic book reader 2700 may have a function of an electronic dictionary.

The electronic book reader 2700 may transmit and receive data wirelessly. The structure can be employed in which a desired book data or the like is purchased and downloaded from an electronic book server wirelessly.

Embodiment 12

A semiconductor device according to the invention disclosed in this specification can be applied to a variety of electronic appliances (including an amusement machine). Examples of electronic appliances are a television set (also referred to as a television or a television receiver), a monitor of a computer or the like, a camera such as a digital camera or a digital video camera, a digital photo frame, a mobile phone handset (also referred to as a mobile phone or a mobile phone device), a portable game console, a portable information terminal, an audio reproducing device, a large-sized game machine such as a pachinko machine, and the like.

FIG. 30A illustrates an example of a television set 9600. In the television set 9600, a display portion 9603 is incorporated in a housing 9601. The display portion 9603 can display an image. Further, the housing 9601 is supported by a stand 9605 here.

The television set 9600 can be operated by an operation switch of the housing 9601 or a separate remote controller 9610. Channels and volume can be controlled by an operation key 9609 of the remote controller 9610 so that an image displayed on the display portion 9603 can be controlled. Further, the remote controller 9610 may be provided with a display portion 9607 for displaying data output from the remote controller 9610.

Note that the television set 9600 is provided with a receiver, a modem, and the like. With the receiver, a general television broadcast can be received. Further, when the television set 9600 is connected to a communication network by wired or wireless connection via the modem, one-way (from a transmitter to a receiver) or two-way (between a transmitter and a receiver or between receivers) data communication can be performed.

FIG. 30B illustrates an example of a digital photo frame 9700. For example, in the digital photo frame 9700, a display portion 9703 is incorporated in a housing 9701. The display portion 9703 can display various images. For example, the display portion 9703 can display data of an image shot by a digital camera or the like to function as a normal photo frame.

Note that the digital photo frame 9700 is provided with an operation portion, an external connection portion (a USB terminal, a terminal that can be connected to various cables such as a USB cable, or the like), a recording medium insertion portion, and the like. Although they may be provided on the surface on which the display portion is provided, it is preferable to provide them on the side surface or the back surface for the design of the digital photo frame 9700. For example, a memory storing data of an image shot by a digital camera is inserted in the recording medium insertion portion of the digital photo frame, whereby the image data can be transferred and then displayed on the display portion 9703.

The digital photo frame 9700 may transmit and receive data wirelessly. The structure may be employed in which desired image data is transferred wirelessly to be displayed.

FIG. 31A is a portable game machine and is constituted by two housings of a housing 9881 and a housing 9891 which are connected with a joint portion 9893 so that the portable game machine can be opened or folded. A display portion 9882 is incorporated in the housing 9881, and a display portion 9883 is incorporated in the housing 9891. In addition, the portable game machine illustrated in FIG. 31A is provided with a speaker portion 9884, a recording medium insert portion 9886, an LED lamp 9890, input means (operation keys 9885, a connection terminal 9887, a sensor 9888 (having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation number, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radial ray, flow rate, humidity, gradient, vibration, odor, or infrared ray), and a microphone 9889), and the like. Needless to say, the structure of the portable game machine is not limited to the described-above. The portable game machine may have a structure in which additional accessory equipment is provided as appropriate as long as at least one embodiment of the semiconductor device according to the present invention is provided. The portable game machine illustrated in FIG. 31A has a function of reading a program or data stored in the recording medium to display it on the display portion, and a function of sharing information with another portable game machine by wireless communication. Note that a function of the portable game machine illustrated in FIG. 31A is not limited to the described-above, and the portable game machine can have a variety of functions.

FIG. 31B illustrates an example of a slot machine 9900 which is a large-sized amusement machine. In the slot machine 9900, a display portion 9903 is incorporated in a housing 9901. In addition, the slot machine 9900 is provided with operation means such as a start lever and a stop switch, a coin slot, a speaker, or the like. Needless to say, the structure of the slot machine 9900 is not limited to the above-described structure. The slot machine may have a structure in which additional accessory equipment is provided as appropriate as long as at least one embodiment of the semiconductor device according to the present invention is provided.

FIG. 32 illustrates an example of a mobile phone handset 1000. The mobile phone handset 1000 is provided with a display portion 1002 incorporated in a housing 1001, operation buttons 1003, an external connection port 1004, a speaker 1005, a microphone 1006, and the like.

When the display portion 1002 illustrated in FIG. 32 is touched with a finger or the like, data can be input into the mobile phone handset 1000. Further, operations such as making calls and composing mails can be performed by touching the display portion 1002 with a finger or the like.

There are mainly three screen modes of the display portion 1002. The first mode is a display mode mainly for displaying an image. The second mode is an input mode mainly for inputting data such as text. The third mode is a display-and-input mode in which two modes of the display mode and the input mode are combined.

For example, in the case of making a call or composing a mail, a text input mode mainly for inputting text is selected for the display portion 1002 so that text displayed on a screen can be inputted. In that case, it is preferable to display a keyboard or number buttons on almost all area of the screen of the display portion 1002.

When a detection device including a sensor for detecting inclination, such as a gyroscope or an acceleration sensor, is provided inside the mobile phone 1000, display in the screen of the display portion 1002 can be automatically switched by determining the direction of the mobile phone 1000 (whether the mobile phone 1000 is placed horizontally or vertically for a landscape mode or portrait mode).

The screen modes are switched by touching the display portion 1002 or operating the operation buttons 1003 of the housing 1001. Alternatively, the screen modes may be switched depending on the kind of the image displayed on the display portion 1002. For example, when a signal of an image displayed on the display portion is the one of moving image data, the screen mode is switched to the display mode. When the signal is the one of text data, the screen mode is switched to the input mode.

Further, in the input mode, when input by touching the display portion 1002 is not performed for a certain period while a signal detected by the optical sensor in the display portion 1002 is detected, the screen mode may be controlled so as to be switched from the input mode to the display mode.

The display portion 1002 may function as an image sensor. For example, an image of the palm print, the fingerprint, or the like is taken by touching the display portion 1002 with the palm or the finger, whereby personal authentication can be performed. Further, by providing a backlight or sensing light source emitting a near-infrared light for the display portion, an image of a finger vein, a palm vein, or the like can be taken.

This application is based on Japanese Patent Application serial no. 2008-197147 filed with Japan Patent Office on Jul. 31, 2008, the entire contents of which are hereby incorporated by reference. 

1. (canceled)
 2. A semiconductor device comprising: a gate electrode layer comprising copper; a gate insulating layer over the gate electrode layer; an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer comprising a channel formation region of a transistor; a first layer over the oxide semiconductor layer; a second layer over the oxide semiconductor layer; a first conductive layer electrically connected to the oxide semiconductor layer through the first layer; and a second conductive layer electrically connected to the oxide semiconductor layer through the second layer, wherein the first conductive layer is configured to function as one of a source electrode layer and a drain electrode layer, wherein the second conductive layer is configured to function as the other of the source electrode layer and the drain electrode layer, wherein, in a cross-sectional view in a channel length direction of the transistor: an edge of the oxide semiconductor layer is provided in a first region beyond an edge of the first layer, the edge of the first layer on the first region side is provided in a region beyond an edge of the first conductive layer, and a film thickness of the oxide semiconductor layer in the first region is smaller than the film thickness of the oxide semiconductor layer in a region overlapping the first layer.
 3. The semiconductor device according to claim 2, wherein the other edge of the oxide semiconductor layer is provided in a second region beyond an edge of the second layer, wherein the edge of the second layer on the second region side is provided in a region beyond an edge of the second conductive layer, and wherein the thickness of the oxide semiconductor layer in the second region is smaller than the thickness of the oxide semiconductor layer in a region overlapping the second layer.
 4. A semiconductor device comprising: a gate electrode layer comprising copper; a gate insulating layer over the gate electrode layer; an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer comprising a channel formation region of a transistor; a first layer over the oxide semiconductor layer; a second layer over the oxide semiconductor layer; a first conductive layer electrically connected to the oxide semiconductor layer through the first layer; and a second conductive layer electrically connected to the oxide semiconductor layer through the second layer, wherein the first conductive layer is configured to function as one of a source electrode layer and a drain electrode layer, wherein the second conductive layer is configured to function as the other of the source electrode layer and the drain electrode layer, wherein, in a plan view: the oxide semiconductor layer comprises a region overlapping with the first layer and a region not overlapping with the first layer, the region not overlapping with the first layer is provided in a periphery of the oxide semiconductor layer, the first layer comprises a region overlapping with the first conductive layer and a region not overlapping with the first conductive layer, the oxide semiconductor layer comprises a region overlapping with the second layer and a region not overlapping with the second layer, the region not overlapping with the second layer is provided in a periphery of the oxide semiconductor layer, the second layer comprises a region overlapping with the second conductive layer and a region not overlapping with the second conductive layer, wherein, in a cross-sectional view in a channel length direction of the transistor: a thickness of the oxide semiconductor layer in the region not overlapping with the first layer is smaller than the thickness of the oxide semiconductor layer in the region overlapping with the first layer, and the thickness of the oxide semiconductor layer in the region not overlapping with the second layer is smaller than the thickness of the oxide semiconductor layer in the region overlapping with the second layer.
 5. A semiconductor device comprising: a gate electrode layer comprising copper; a gate insulating layer over the gate electrode layer; an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer comprising a channel formation region of a transistor; a first layer over the oxide semiconductor layer; a second layer over the oxide semiconductor layer; a first conductive layer electrically connected to the oxide semiconductor layer through the first layer; and a second conductive layer electrically connected to the oxide semiconductor layer through the second layer, wherein the first conductive layer is configured to function as one of a source electrode layer and a drain electrode layer, wherein the second conductive layer is configured to function as the other of the source electrode layer and the drain electrode layer, wherein, in a cross-sectional view in a channel length direction of the transistor: the oxide semiconductor layer has a depression in the channel formation region, and an edge of the first layer on the side of the depression is provided in a region beyond an edge of the first conductive layer
 6. The semiconductor device according to claim 2, wherein the first layer comprises indium and zinc.
 7. The semiconductor device according to claim 4, wherein the first layer comprises indium and zinc.
 8. The semiconductor device according to claim 5, wherein the first layer comprises indium and zinc.
 9. The semiconductor device according to claim 6, wherein the second layer comprises indium and zinc.
 10. The semiconductor device according to claim 7, wherein the second layer comprises indium and zinc.
 11. The semiconductor device according to claim 8, wherein the second layer comprises indium and zinc.
 12. The semiconductor device according to claim 9, wherein a carrier density of the first layer is higher than the carrier density of the oxide semiconductor layer.
 13. The semiconductor device according to claim 10, wherein a carrier density of the first layer is higher than the carrier density of the oxide semiconductor layer.
 14. The semiconductor device according to claim 11, wherein a carrier density of the first layer is higher than the carrier density of the oxide semiconductor layer.
 15. The semiconductor device according to claim 12, wherein a carrier density of the second layer is higher than the carrier density of the oxide semiconductor layer.
 16. The semiconductor device according to claim 13, wherein a carrier density of the second layer is higher than the carrier density of the oxide semiconductor layer.
 17. The semiconductor device according to claim 14, wherein a carrier density of the second layer is higher than the carrier density of the oxide semiconductor layer.
 18. The semiconductor device according to claim 15, wherein the first conductive layer and the second conductive layer comprise copper, and wherein an insulating layer provided over the transistor is in contact with a region of the channel formation region.
 19. The semiconductor device according to claim 16, wherein the first conductive layer and the second conductive layer comprise copper, and wherein an insulating layer provided over the transistor is in contact with a region of the channel formation region.
 20. The semiconductor device according to claim 17, wherein the first conductive layer and the second conductive layer comprise copper, and wherein an insulating layer provided over the transistor is in contact with a region of the channel formation region. 